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formal_hw_verification
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6 Commits (b8a39e910623ca9300150ee0f6a79d23746cb96c)

Author SHA1 Message Date
  T. Meissner 60e2c0f301 Add some more signals to trace 7 years ago
  T. Meissner b48e99c1f0 Simplify signal generation 7 years ago
  T. Meissner 4e30f44cb0 Fix req cai handling; add more properties 7 years ago
  T. Meissner 1deb6e9789 Add vai_reg to README; using SVA default clocking 7 years ago
  T. Meissner 63fc34f66a Add DoutValid_o to condition for state change in putput states 7 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 7 years ago