Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl
verilog
assertions
formal
yosys
systemverilog
sva

Makefile 193B

12345678910111213
  1. DESIGNS := $(shell cat tests.txt)
  2. .PHONY: ${DESIGNS} all clean
  3. all: ${DESIGNS}
  4. $(DESIGNS):
  5. make -C $@ all -j$(nproc)
  6. clean:
  7. for dir in $(DESIGNS); do \
  8. make -C $$dir clean; \
  9. done