Trying to verify Verilog/VHDL designs with formal methods and tools
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
 

13 lines
193 B

DESIGNS := $(shell cat tests.txt)
.PHONY: ${DESIGNS} all clean
all: ${DESIGNS}
$(DESIGNS):
make -C $@ all -j$(nproc)
clean:
for dir in $(DESIGNS); do \
make -C $$dir clean; \
done