Trying to verify Verilog/VHDL designs with formal methods and tools
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30 lines
576 B

depth 20
cover: mode cover
bmc: mode bmc
prove: mode prove
cover: smtbmc z3
bmc: abc bmc3
prove: abc pdr
ghdl --std=08 -gFormal=true -gDepth=8 -gWidth=4 fifo.vhd fwft_fifo.vhd -e fwft_fifo
prep -top fwft_fifo
# Convert all assumes to asserts in sub-units
chformal -assume2assert fwft_fifo/* %M
# Remove selected covers in i_fifo sub-unit as they cannot be reached
chformal -cover -remove */formalg.read_pnt_stable_when_empty.cover
chformal -cover -remove */formalg.rerror.cover