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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/counter
T. Meissner d94585cad8 Making counter design work with GHDL synthesis 5 years ago
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Makefile Making counter design work with GHDL synthesis 5 years ago
counter.vhd Making counter design work with GHDL synthesis 5 years ago
symbiyosys.sby Making counter design work with GHDL synthesis 5 years ago