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355 lines
10 KiB
355 lines
10 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vai_reg is
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generic (
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Formal : boolean := true
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);
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port (
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Reset_n_i : in std_logic;
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Clk_i : in std_logic;
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-- req
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Din_i : in std_logic_vector(7 downto 0);
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DinValid_i : in std_logic;
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DinStart_i : in std_logic;
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DinStop_i : in std_logic;
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DinAccept_o : out std_logic;
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-- ack
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Dout_o : out std_logic_vector(7 downto 0);
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DoutValid_o : out std_logic;
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DoutStart_o : out std_logic;
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DoutStop_o : out std_logic;
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DoutAccept_i : in std_logic
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);
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end entity vai_reg;
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architecture rtl of vai_reg is
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constant C_READ : std_logic_vector(3 downto 0) := x"0";
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constant C_WRITE : std_logic_vector(3 downto 0) := x"1";
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type t_fsm_state is (IDLE, GET_HEADER, GET_DATA,
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SET_DATA, SEND_HEADER, SEND_DATA, SEND_FOOTER);
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signal s_fsm_state : t_fsm_state;
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type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
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signal s_register : t_register;
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signal s_header : std_logic_vector(7 downto 0);
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signal s_data : std_logic_vector(7 downto 0);
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signal s_error : boolean;
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signal s_dout_accepted : boolean;
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alias a_addr : std_logic_vector(3 downto 0) is s_header(7 downto 4);
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begin
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s_dout_accepted <= (DoutValid_o and DoutAccept_i) = '1';
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process (Reset_n_i, Clk_i) is
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begin
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if (Reset_n_i = '0') then
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DinAccept_o <= '0';
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DoutStart_o <= '0';
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DoutStop_o <= '0';
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DoutValid_o <= '0';
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Dout_o <= (others => '0');
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s_header <= (others => '0');
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s_data <= (others => '0');
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s_register <= (others => (others => '0'));
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s_error <= false;
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s_fsm_state <= IDLE;
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elsif (rising_edge(Clk_i)) then
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case s_fsm_state is
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when IDLE =>
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DinAccept_o <= '0';
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DoutStart_o <= '0';
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DoutStop_o <= '0';
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DoutValid_o <= '0';
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Dout_o <= (others => '0');
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s_header <= (others => '0');
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s_data <= (others => '0');
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s_error <= false;
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DinAccept_o <= '1';
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s_fsm_state <= GET_HEADER;
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when GET_HEADER =>
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if (DinValid_i = '1' and DinStart_i = '1') then
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s_header <= Din_i;
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if (Din_i(3 downto 0) = C_READ and DinStop_i = '1') then
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DinAccept_o <= '0';
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s_fsm_state <= GET_DATA;
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elsif (Din_i(3 downto 0) = C_WRITE and DinStop_i = '0') then
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s_fsm_state <= SET_DATA;
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else
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DinAccept_o <= '0';
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s_fsm_state <= IDLE;
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end if;
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end if;
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when GET_DATA =>
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if (unsigned(a_addr) <= 7) then
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s_data <= s_register(to_integer(unsigned(a_addr)));
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else
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s_error <= true;
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s_data <= (others => '0');
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end if;
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s_fsm_state <= SEND_HEADER;
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when SET_DATA =>
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if (DinValid_i = '1') then
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DinAccept_o <= '0';
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if (DinStop_i = '1') then
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if (unsigned(a_addr) <= 7) then
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s_register(to_integer(unsigned(a_addr))) <= Din_i;
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else
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s_error <= true;
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end if;
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s_fsm_state <= SEND_HEADER;
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else
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s_fsm_state <= IDLE;
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end if;
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end if;
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when SEND_HEADER =>
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DoutValid_o <= '1';
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DoutStart_o <= '1';
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Dout_o <= s_header;
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if (s_dout_accepted) then
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DoutValid_o <= '0';
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DoutStart_o <= '0';
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if (s_header(3 downto 0) = C_WRITE) then
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s_fsm_state <= SEND_FOOTER;
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else
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s_fsm_state <= SEND_DATA;
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end if;
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end if;
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when SEND_DATA =>
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DoutValid_o <= '1';
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Dout_o <= s_data;
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if (s_dout_accepted) then
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DoutValid_o <= '0';
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s_fsm_state <= SEND_FOOTER;
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end if;
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when SEND_FOOTER =>
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DoutValid_o <= '1';
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DoutStop_o <= '1';
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Dout_o <= x"01" when s_error else x"00";
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if (s_dout_accepted) then
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Dout_o <= (others => '0');
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DoutValid_o <= '0';
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DoutStop_o <= '0';
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s_fsm_state <= IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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FormalG : if Formal generate
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signal s_addr : natural range 0 to 15;
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type t_cmd is (READ, WRITE, NOP);
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signal s_cmd : t_cmd;
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begin
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-- VHDL helper logic
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process is
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begin
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wait until rising_edge(Clk_i);
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if (s_fsm_state = GET_HEADER) then
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if (DinValid_i = '1' and DinStart_i = '1') then
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s_cmd <= READ when Din_i(3 downto 0) = x"0" else
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WRITE when Din_i(3 downto 0) = x"1" else
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NOP;
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s_addr <= to_integer(unsigned(Din_i(7 downto 4)));
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end if;
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end if;
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end process;
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default clock is rising_edge(Clk_i);
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-- RESTRICTIONS
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-- Initial reset
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INITIAL_RESET : restrict {not Reset_n_i[*2]; Reset_n_i[+]}[*1];
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-- CONSTRAINTS
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-- Valid stable until accepted
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JOB_REQ_VALID_STABLE : assume always
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DinValid_i and not DinAccept_o -> next (stable(DinValid_i) until_ DinAccept_o);
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-- Start stable until accepted
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JOB_REQ_START_STABLE : assume always
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DinValid_i and not DinAccept_o -> next (stable(DinStart_i) until_ DinAccept_o);
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-- Stop stable until accepted
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JOB_REQ_STOP_STABLE : assume always
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DinValid_i and not DinAccept_o -> next (stable(DinStop_i) until_ DinAccept_o);
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-- Data stable until accepted
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JOB_REQ_DIN_STABLE : assume always
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DinValid_i and not DinAccept_o -> next (stable(Din_i) until_ DinAccept_o);
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-- ASSERTIONS
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-- Reset values
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AFTER_RESET : assert always
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not Reset_n_i
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->
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s_fsm_state = IDLE and
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not DinAccept_o and
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not DoutStart_o and
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not DoutStop_o and
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not DoutValid_o and
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s_register = (0 to 7 => x"00");
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-- FSM states in valid range
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FSM_STATES_VALID : assert always
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s_fsm_state = IDLE or s_fsm_state = GET_HEADER or
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s_fsm_state = GET_DATA or s_fsm_state = SET_DATA or
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s_fsm_state = SEND_HEADER or s_fsm_state = SEND_DATA or
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s_fsm_state = SEND_FOOTER;
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-- Discard jobs with invalid command
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INV_CMD_DISCARD : assert always
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s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and
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Din_i(3 downto 0) /= x"0" and Din_i(3 downto 0) /= x"1"
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->
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next s_fsm_state = IDLE;
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-- Discard read job with invalid stop flags
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READ_INV_FLAGS_DISCARD : assert always
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s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and
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Din_i(3 downto 0) = x"0" and DinStop_i = '0'
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->
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next s_fsm_state = IDLE;
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-- Discard write job with invalid stop flags
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WRITE_INV_FLAGS_DISCARD : assert always
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s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and
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Din_i(3 downto 0) = x"1" and DinStop_i = '1'
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->
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next s_fsm_state = IDLE;
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-- After a valid job read request,
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-- a job read acknowledge has to follow
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READ_VALID_ACK : assert always
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{s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and
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Din_i(3 downto 0) = x"0" and DinStop_i = '1'}
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|=>
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{-- Job ack header cycle
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not DoutValid_o [*];
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DoutValid_o and DoutStart_o and not DoutAccept_i [*];
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DoutValid_o and DoutStart_o and DoutAccept_i;
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-- Job ack data cycle
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not DoutValid_o [*];
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DoutValid_o and not DoutStart_o and not DoutStop_o and not DoutAccept_i [*];
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DoutValid_o and not DoutStart_o and not DoutStop_o and DoutAccept_i;
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-- Job ack footer cycle
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not DoutValid_o [*];
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DoutValid_o and DoutStop_o};
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-- After a valid job write request,
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-- a job read acknowledge has to follow
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WRITE_VALID_ACK : assert always
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{s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and
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Din_i(3 downto 0) = x"1" and DinStop_i = '0';
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not DinValid_i [*];
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DinValid_i and DinStop_i}
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|=>
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{-- Job ack header cycle
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not DoutValid_o [*];
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DoutValid_o and DoutStart_o and not DoutAccept_i [*];
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DoutValid_o and DoutStart_o and DoutAccept_i;
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-- Job ack footer cycle
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not DoutValid_o [*];
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DoutValid_o and DoutStop_o};
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-- Start & stop flag have to be exclusive
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JOB_ACK_NEVER_START_STOP : assert never
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DoutStart_o and DoutStop_o;
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-- Start & Stop have to be active together with valid
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JOB_ACK_START_STOP_VALID : assert always
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DoutStart_o or DoutStop_o -> DoutValid_o;
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-- Valid has to be stable until accepted
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JOB_ACK_VALID_STABLE : assert always
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DoutValid_o and not DoutAccept_i -> next (stable(DoutValid_o) until_ DoutAccept_i);
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-- Start has to be stable until accepted
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JOB_ACK_START_STABLE : assert always
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DoutValid_o and not DoutAccept_i -> next (stable(DoutStart_o) until_ DoutAccept_i);
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-- Stop has to be stable until accepted
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JOB_ACK_STOP_STABLE : assert always
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DoutValid_o and not DoutAccept_i -> next (stable(DoutStop_o) until_ DoutAccept_i);
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-- Data has to be stable until accepted
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JOB_ACK_DOUT_STABLE : assert always
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DoutValid_o and not DoutAccept_i -> next (stable(Dout_o) until_ DoutAccept_i);
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-- Data from selected address has to be read
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READ_DATA : assert always
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DoutValid_o and not DoutStart_o and not DoutStop_o and s_addr <= 7
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->
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Dout_o = s_register(s_addr);
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-- 0 has to be read when invalid address is given
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READ_DATA_INV_ADDR : assert always
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DoutValid_o and not DoutStart_o and not DoutStop_o and s_addr > 7
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->
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Dout_o = x"00";
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-- Register has to be written at given address with given data
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-- when correct job req write occurs
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WRITE_DATA : assert always
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-- Job req header cycle
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{s_fsm_state = GET_HEADER and DinValid_i = '1' and DinStart_i = '1' and
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Din_i(3 downto 0) = x"1" and unsigned(Din_i(7 downto 4)) <= 7 and DinStop_i = '0';
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-- Job req data / footer cycle
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not DinValid_i [*];
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DinValid_i and not DinStart_i and DinStop_i and not DinAccept_o [*];
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DinValid_i and not DinStart_i and DinStop_i and DinAccept_o}
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|=>
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{s_register(s_addr) = prev(Din_i)};
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-- FUNCTIONAL COVERAGE
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FOOTER_VALID : cover {DoutValid_o = '1' and DoutStop_o = '1' and Dout_o = 8x"0"};
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FOOTER_ERR : cover {DoutValid_o = '1' and DoutStop_o = '1' and Dout_o = 8x"1"};
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end generate FormalG;
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end architecture rtl;
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