tmeissner
/
formal_hw_verification
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 6 Wiki Activity
52 Commits
3 Branches
324 KiB
Tree: 2bc122eb5d
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '2bc122eb5d'
${ noResults }
Commit Graph

10 Commits (2bc122eb5d5b76a72e0825006dc7fad1842ba1e0)

Author SHA1 Message Date
  T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 5 years ago
  T. Meissner 6c3a6db83b Remove unused SVA properties file; Makefile optimizations; use prep auto-top option to prevent error with not founded top-level module 5 years ago
  T. Meissner bd5fcbcb7a GHDL supports memory with resets, finally 5 years ago
  T. Meissner e71b70d34e Add Assumptions about job req VAI interface 5 years ago
  T. Meissner 8cf0be6e4c Add many new asserts & covers 5 years ago
  T. Meissner 195765a2aa Adapt to use GHDL as plugin for Yosys VHDL synthesis 5 years ago
  T. Meissner b48e99c1f0 Simplify signal generation 6 years ago
  T. Meissner 4e30f44cb0 Fix req cai handling; add more properties 6 years ago
  T. Meissner 63fc34f66a Add DoutValid_o to condition for state change in putput states 6 years ago
  T. Meissner a0f6a0b81d Add simple VAI register file as base to try to formal verify FSM designs 6 years ago