tmeissner/formal_hw_verification: Trying to verify Verilog/VHDL designs with formal methods and tools - counter/Makefile at 60e2c0f301870db303db5c260117888dad9d7c43 - formal_hw_verification - goodcleanfun Gitea

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog assertions formal yosys systemverilog sva

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 								.PHONY: counter
 								counter: counter.vhd counter_t.sv counter_f.sby
 									sby -f -d work counter_f.sby
 								.PHONY: clean
 								clean:
 									rm -rf work