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167 lines
3.5 KiB
167 lines
3.5 KiB
module properties (
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input Reset_n_i,
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input Clk_i,
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input [7:0] Din_i,
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input DinValid_i,
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input DinStart_i,
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input DinStop_i,
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input DinAccept_o,
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input [7:0] Dout_o,
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input DoutValid_o,
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input DoutStart_o,
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input DoutStop_o,
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input DoutAccept_i,
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// Internals
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input [2:0] s_fsm_state,
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input [7:0] s_header
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);
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`define READ 0
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`define WRITE 1
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reg init_state = 1;
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// Initial reset
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always @(*) begin
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if (init_state) assume (!Reset_n_i);
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if (!init_state) assume (Reset_n_i);
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end
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always @(posedge Clk_i)
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init_state = 0;
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// Constraints
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assume property (@(posedge Clk_i)
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DinValid_i && !DinAccept_o |=>
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$stable(Din_i)
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);
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assume property (@(posedge Clk_i)
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DinValid_i && !DinAccept_o |=>
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$stable(DinStart_i)
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);
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assume property (@(posedge Clk_i)
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DinValid_i && !DinAccept_o |=>
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$stable(DinStop_i)
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);
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// Asserts
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assert property (@(posedge Clk_i)
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s_fsm_state >= 0 && s_fsm_state <= 6
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);
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assert property (@(posedge Clk_i)
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DoutStart_o |->
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DoutValid_o
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);
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assert property (@(posedge Clk_i)
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DoutStart_o && DoutAccept_i |=>
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!DoutStart_o
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);
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assert property (@(posedge Clk_i)
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DoutStop_o |->
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DoutValid_o
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);
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assert property (@(posedge Clk_i)
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DoutStop_o && DoutAccept_i |=>
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!DoutStop_o
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);
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assert property (@(posedge Clk_i)
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s_fsm_state == 1 && DinValid_i && DinStart_i && DinAccept_o |=>
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s_header == $past(Din_i)
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);
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// State changes
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 0 |=> s_fsm_state == 1
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);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 1 && DinValid_i && DinStart_i && DinStop_i && Din_i[3:0] == `READ |=>
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s_fsm_state == 2
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);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 1 && DinValid_i && DinStart_i && !DinStop_i && Din_i[3:0] == `WRITE |=>
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s_fsm_state == 3
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);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 2 |=> s_fsm_state == 4
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);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 4 && DoutValid_o && DoutAccept_i && s_header[3:0] == `READ |=> s_fsm_state == 5
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);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 4 && DoutValid_o && DoutAccept_i && s_header[3:0] != `READ |=> s_fsm_state == 6
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);
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assert property (@(posedge Clk_i) disable iff (!Reset_n_i)
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s_fsm_state == 6 && DoutValid_o && DoutAccept_i |=> s_fsm_state == 0
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);
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// Protocol checks
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assert property (@(posedge Clk_i)
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s_fsm_state > 1 |->
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s_header[3:0] == `READ || s_header[3:0] == `WRITE
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);
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assert property (@(posedge Clk_i)
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DoutStart_o && DoutValid_o |->
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Dout_o[3:0] == s_header[3:0]
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);
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assert property (@(posedge Clk_i)
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DoutValid_o && !DoutAccept_i |=>
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$stable(Dout_o)
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);
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assert property (@(posedge Clk_i)
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DoutValid_o && !DoutAccept_i |=>
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$stable(DoutStart_o)
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);
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assert property (@(posedge Clk_i)
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DoutValid_o && !DoutAccept_i |=>
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$stable(DoutStop_o)
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);
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assert property (@(posedge Clk_i)
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DoutValid_o |-> !(DoutStart_o && DoutStop_o)
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);
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assert property (@(posedge Clk_i)
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DoutStart_o |-> s_fsm_state == 4
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);
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assert property (@(posedge Clk_i)
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DoutStop_o |-> s_fsm_state == 6
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);
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assert property (@(posedge Clk_i)
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DoutValid_o |-> s_fsm_state >= 4 && s_fsm_state <= 6
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);
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endmodule
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bind vai_reg properties properties (.*);
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