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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/counter
T. Meissner f2f433b165 Use PSL functions instead of workarounds; add forgotten always to asserts in alu 4 years ago
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Makefile Making counter design work with GHDL synthesis 4 years ago
counter.vhd Use PSL functions instead of workarounds; add forgotten always to asserts in alu 4 years ago
symbiyosys.sby Making counter design work with GHDL synthesis 4 years ago