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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/vai_reg
T. Meissner 9cb4b7d291 Replace integer coded FSM states by symbolic state names 6 years ago
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Makefile Add simple VAI register file as base to try to formal verify FSM designs 6 years ago
properties.sv Replace integer coded FSM states by symbolic state names 6 years ago
symbiyosys.sby Add simple VAI register file as base to try to formal verify FSM designs 6 years ago
trace.gtkw Add some more signals to trace 6 years ago
vai_reg.vhd Simplify signal generation 6 years ago