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formal_hw_verification
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Trying to verify Verilog/VHDL designs with formal methods and tools
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formal_hw_verification/vai_reg
T. Meissner e71b70d34e Add Assumptions about job req VAI interface 5 years ago
..
doc Add png versions of read/write waveform examples 6 years ago
Makefile Add make targets and SymbiYosys tasks for cover, bmc & prove 5 years ago
properties.sv Replace integer coded FSM states by symbolic state names 6 years ago
symbiyosys.sby Add make targets and SymbiYosys tasks for cover, bmc & prove 5 years ago
trace.gtkw Add some more signals to trace 6 years ago
vai_reg.vhd Add Assumptions about job req VAI interface 5 years ago