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@ -29,8 +29,6 @@ architecture rtl of blink is |
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signal s_rst_n : std_logic; |
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signal s_rst_n : std_logic; |
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signal s_cfg_end : std_logic; |
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signal s_cfg_end : std_logic; |
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signal s_led : unsigned(led_n_o'range); |
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begin |
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begin |
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pll : CC_PLL |
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pll : CC_PLL |
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@ -74,14 +72,12 @@ begin |
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process (s_pll_clk, s_rst_n) is |
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process (s_pll_clk, s_rst_n) is |
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begin |
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begin |
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if (not s_rst_n) then |
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if (not s_rst_n) then |
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s_led <= x"01"; |
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led_n_o <= x"FE"; |
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elsif (rising_edge(s_pll_clk)) then |
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elsif (rising_edge(s_pll_clk)) then |
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if (s_clk_en) then |
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if (s_clk_en) then |
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s_led <= s_led(6 downto 0) & s_led(7); |
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led_n_o <= led_n_o(6 downto 0) & led_n_o(7); |
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end if; |
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end if; |
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end if; |
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end if; |
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end process; |
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end process; |
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led_n_o <= not std_logic_vector(s_led); |
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end architecture; |
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end architecture; |
