Add inital version of uart register test design

uart/rtl/uart_reg.vhd

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+-- This design should display incrementing binary numbers
+-- at LED1-LED8 of the GateMate FPGA Starter Kit.
+
+
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library gatemate;
+use gatemate.components.all;
+
+
+entity uart_reg is
+port (
+  clk_i     : in  std_logic;                    -- 10 MHz clock
+  rst_n_i   : in  std_logic;                    -- SW3 button
+  uart_rx_i : in  std_logic;
+  uart_tx_o : out std_logic;
+  led_n_o   : out std_logic_vector(2 downto 0)  -- LED1..LED2
+);
+end entity uart_reg;
+
+
+architecture rtl of uart_reg is
+
+  signal s_pll_clk  : std_logic;
+  signal s_pll_lock : std_logic;
+  signal s_clk_en   : boolean;
+
+  signal s_rst_n   : std_logic;
+  signal s_cfg_end : std_logic;
+
+begin
+
+  pll : CC_PLL
+  generic map (
+    REF_CLK => "10",
+    OUT_CLK => "1",
+    PERF_MD => "ECONOMY"
+  )
+  port map (
+    CLK_REF             => clk_i,
+    CLK_FEEDBACK        => '0',
+    USR_CLK_REF         => '0',
+    USR_LOCKED_STDY_RST => '0',
+    USR_PLL_LOCKED_STDY => open,
+    USR_PLL_LOCKED      => s_pll_lock,
+    CLK270              => open,
+    CLK180              => open,
+    CLK0                => s_pll_clk,
+    CLK90               => open,
+    CLK_REF_OUT         => open
+  );
+
+  cfg_end_inst : CC_CFG_END
+  port map (
+    CFG_END => s_cfg_end
+  );
+
+  s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
+
+  -- Start with simple loop
+  uart_tx_o <= uart_rx_i;
+
+  -- Debug output
+  led_n_o <= s_rst_n & not (s_pll_lock, s_cfg_end);
+
+end architecture;

uart/syn/Makefile

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+DESIGN_NAME := uart_reg
+WORK_FILES   := ../rtl/uart_reg.vhd
+GM_FILES    := ../../lib/components.vhd
+GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
+YOSYSPIPE   := -nomx8 -luttree -retime
+PNRFLAGS    := -sp off -om 2 -cCP on
+PNRTOOL     := $(shell which p_r)
+
+.PHONY: all syn imp prog
+
+all: imp
+syn: ${DESIGN_NAME}.v
+imp: ${DESIGN_NAME}.bit
+
+build/work-obj08.cf: ${WORK_FILES} build/gatemate-obj08.cf
+	ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES}
+
+build/gatemate-obj08.cf: ${GM_FILES}
+	mkdir -p build
+	ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
+
+${DESIGN_NAME}.v: build/work-obj08.cf
+	yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
+	  2>&1 | tee build/yosys-report.txt
+
+${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
+	cd build && \
+	  ${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \
+	  2>&1 | tee p_r-report.txt && \
+	  mv ${DESIGN_NAME}*.bit ../$@
+
+prog: ${DESIGN_NAME}.bit
+	openFPGALoader -b gatemate_evb_jtag $<
+
+clean :
+	echo "# Cleaning files"
+	rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.bit

uart/syn/uart_reg.ccf

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+# Configuration for the Gatemate eval board
+
+Pin_in   "clk_i"   Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
+Pin_in   "rst_n_i" Loc = "IO_EB_B0"; # SW3
+
+Pin_out  "led_n_o[0]"  Loc = "IO_EB_B1"; # LED D1
+Pin_out  "led_n_o[1]"  Loc = "IO_EB_B2"; # LED D2
+Pin_out  "led_n_o[2]"  Loc = "IO_EB_B3"; # LED D3
+#Pin_out  "led_n_o[3]"  Loc = "IO_EB_B4"; # LED D4
+#Pin_out  "led_n_o[4]"  Loc = "IO_EB_B5"; # LED D5
+#Pin_out  "led_n_o[5]"  Loc = "IO_EB_B6"; # LED D6
+#Pin_out  "led_n_o[6]"  Loc = "IO_EB_B7"; # LED D7
+#Pin_out  "led_n_o[7]"  Loc = "IO_EB_B8"; # LED D8
+
+Pin_in   "uart_rx_i"  Loc = "IO_NB_A1"; # PMODA IO3
+Pin_out  "uart_tx_o"  Loc = "IO_NB_A2"; # PMODA IO5