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37 lines
1.1 KiB
37 lines
1.1 KiB
DESIGN_NAME := uart_reg
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WORK_FILES := ../rtl/uart_reg.vhd
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GM_FILES := ../../lib/components.vhd
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GHDL_FLAGS := --std=08 --workdir=build -Pbuild
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YOSYSPIPE := -nomx8 -luttree -retime
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PNRFLAGS := -sp off -om 2 -cCP on
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PNRTOOL := $(shell which p_r)
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.PHONY: all syn imp prog
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all: imp
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syn: ${DESIGN_NAME}.v
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imp: ${DESIGN_NAME}.bit
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build/work-obj08.cf: ${WORK_FILES} build/gatemate-obj08.cf
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ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES}
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build/gatemate-obj08.cf: ${GM_FILES}
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mkdir -p build
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ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
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${DESIGN_NAME}.v: build/work-obj08.cf
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yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
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2>&1 | tee build/yosys-report.txt
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${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
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cd build && \
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${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \
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2>&1 | tee p_r-report.txt && \
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mv ${DESIGN_NAME}*.bit ../$@
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prog: ${DESIGN_NAME}.bit
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openFPGALoader -b gatemate_evb_jtag $<
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clean :
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echo "# Cleaning files"
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rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.bit
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