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gatemate_experiments
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1 Commits (100363411076524a8d0fe6367ffa992b0f0d95a8)

Author SHA1 Message Date
  T. Meissner 1003634110 Add inital version of uart register test design 2 years ago
  T. Meissner a0fcc51dc8 Add make target to program FPGA 2 years ago
  T. Meissner f28d35d12b Also remove bit file in clean target 2 years ago
  T. Meissner efaca0c912 Add PnR pass and constraint file 2 years ago
  T. Meissner 95887cb31d Add PLL to blink design 2 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 2 years ago