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@ -6,6 +6,9 @@ library ieee ; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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library gatemate; |
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use gatemate.components.all; |
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entity blink is |
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port ( |
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@ -18,14 +21,36 @@ end entity blink; |
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architecture rtl of blink is |
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signal s_clk_cnt : unsigned(19 downto 0); |
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signal s_clk_en : boolean; |
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signal s_pll_clk : std_logic; |
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signal s_pll_lock : std_logic; |
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signal s_clk_cnt : unsigned(19 downto 0); |
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signal s_clk_en : boolean; |
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signal s_led : unsigned(led_n_o'range); |
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begin |
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process (clk_i, rst_n_i) is |
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pll : CC_PLL |
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generic map ( |
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REF_CLK => "10", |
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OUT_CLK => "1", |
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PERF_MD => "SPEED" |
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) |
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port map ( |
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CLK_REF => clk_i, |
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CLK_FEEDBACK => '0', |
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USR_CLK_REF => '0', |
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USR_LOCKED_STDY_RST => not rst_n_i, |
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USR_PLL_LOCKED_STDY => open, |
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USR_PLL_LOCKED => s_pll_lock, |
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CLK270 => open, |
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CLK180 => open, |
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CLK0 => open, |
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CLK90 => open, |
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CLK_REF_OUT => s_pll_clk |
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); |
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process (s_pll_clk, rst_n_i) is |
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begin |
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if (not rst_n_i) then |
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s_clk_cnt <= (others => '0'); |
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@ -36,7 +61,7 @@ begin |
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s_clk_en <= s_clk_cnt = (s_clk_cnt'range => '1'); |
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process (clk_i, rst_n_i) is |
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process (s_pll_clk, rst_n_i) is |
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begin |
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if (not rst_n_i) then |
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s_led <= (others => '0'); |
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