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gatemate_experiments
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  • 5d9943c (HEAD -> main) Remove CC_CTRL_END component, use CC_USR_RSTN instead by tmeissner 2023-11-16 15:10:19 +0100
  • bb98b0e Add comments with some hints to yosys & p_r options and their effects by tmeissner 2023-02-01 18:25:10 +0100
  • 9c353f3 Remove unused local neorv32_top; adapt neorv32_aes top-level by tmeissner 2023-02-01 18:23:47 +0100
  • 6b1b376 Use speed instead of moderate FPGA speed grade by tmeissner 2023-01-30 16:05:27 +0100
  • e845a0d Bring back neorv32_aes.vhd, which was wrongly deleted by tmeissner 2023-01-09 10:15:10 +0100
  • d982691 Update neorv32 submodule by tmeissner 2023-01-08 22:11:55 +0100
  • 3ae59c3 Use neorv-repo top level instead of local one by tmeissner 2023-01-08 22:11:34 +0100
  • bf6508d Add info about neorv32_aes and uart_aes to README by tmeissner 2023-01-06 23:11:55 +0100
  • 89730f7 Use random stimuli in uart_loop testbench by tmeissner 2023-01-06 22:35:44 +0100
  • 1777fbd Add uart_aes design, simulation & fpga-flow by tmeissner 2023-01-06 22:35:06 +0100
  • f8ba0b1 Add VHDL sim for RTL & Verilog sim for post-syn simulation by tmeissner 2023-01-05 19:29:44 +0100
  • b8d7ecd Update neorv32_aes top level; Add some iverilog options by tmeissner 2023-01-05 19:28:29 +0100
  • 84f2515 Update neorv32 submodule by tmeissner 2023-01-05 19:17:17 +0100
  • b01669c Update Makefile to build cryptocores AES-CTR component by tmeissner 2023-01-02 20:08:07 +0100
  • 194f4c7 Update neorv32 submodule by tmeissner 2023-01-02 20:07:15 +0100
  • ab480c6 Remove old neorv32 top level, neorv32_aes is used instead now by tmeissner 2023-01-02 20:03:52 +0100
  • dfd0a59 Add cryptocores as git submodule by tmeissner 2023-01-02 18:36:54 +0100
  • dc0e1aa Update top-level & Makefile to use new AES CF module by tmeissner 2023-01-02 16:56:17 +0100
  • 70f13ef Update neorv32 submodule by tmeissner 2023-01-02 16:46:11 +0100
  • 99971e7 We have a config with uart which gatemate p_r-tool can handle by tmeissner 2022-12-31 12:51:30 +0100
  • ee77f92 Add CC_BRAM_20K and CC_BRAM_40K to rtl components package by tmeissner 2022-12-31 12:49:57 +0100
  • 4cc4aa2 Add neorv32_aes design by tmeissner 2022-12-31 01:23:39 +0100
  • d9b1dfc Add fork of neorv32 with AES CFS as git submodule by tmeissner 2022-12-31 00:26:26 +0100
  • b2e9cf5 Remove unneeded synthesis attributes for ring oscillator by tmeissner 2022-12-30 21:46:08 +0100
  • 0df7a04 Add uart_trng design by tmeissner 2022-12-30 21:40:59 +0100
  • 32fa71a Increase pll clock to 10 MHz, add uart_loop design to readme by tmeissner 2022-12-30 18:47:20 +0100
  • 3cfa3cc Add uart_loop design to test gatemate fifo & ram primitives by tmeissner 2022-12-30 15:50:53 +0100
  • 9a275ee Update README by tmeissner 2022-12-29 17:41:15 +0100
  • d63dfe6 Update uart_reg to full reg file implementation by tmeissner 2022-12-29 17:25:03 +0100
  • 8cf0e61 blink & uart_reg designs are working now by tmeissner 2022-12-29 14:45:58 +0100
  • a3cabb7 Refactoring of CC_PLL simulation model by tmeissner 2022-12-28 14:22:31 +0100
  • 3b6a315 Add user_components.vhd containing generic RTL modules by tmeissner 2022-12-28 12:23:15 +0100
  • 6cffeef Rename components.vhd to rtl_components.vhd by tmeissner 2022-12-28 10:22:37 +0100
  • 61affc8 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations by tmeissner 2022-12-28 00:16:38 +0100
  • 0e84416 Rename uart folder to uart_reg by tmeissner 2022-12-27 11:37:38 +0100
  • 1003634 Add inital version of uart register test design by tmeissner 2022-12-27 11:32:37 +0100
  • cfa6f88 Add simple gatemate primitives simulation components by tmeissner 2022-12-27 01:16:48 +0100
  • 012de1f RTL refactoring by tmeissner 2022-12-27 01:08:46 +0100
  • d57f683 Adapt sim to updated RTL by tmeissner 2022-12-27 01:02:47 +0100
  • 133e25a Let LEDs rotate instead of counting up by tmeissner 2022-12-27 00:11:58 +0100
  • a0fcc51 Add make target to program FPGA by tmeissner 2022-12-27 00:09:06 +0100
  • eb0d52e Add blink design info and more links to README by tmeissner 2022-12-23 16:51:46 +0100
  • 81be6cf (blink_with_pll) Add CC_CFG_END unit, Use PLL lock & cfg_end for reset by tmeissner 2022-12-23 16:39:24 +0100
  • f28d35d Also remove bit file in clean target by tmeissner 2022-12-23 16:38:35 +0100
  • efaca0c Add PnR pass and constraint file by tmeissner 2022-12-23 11:58:33 +0100
  • 95887cb Add PLL to blink design by tmeissner 2022-12-23 02:40:12 +0100
  • 45ced01 Add blink design & simulation by tmeissner 2022-12-23 00:52:24 +0100
  • a38eedb Add license by tmeissner 2022-12-22 19:18:20 +0100
  • eea3893 Fix readme by tmeissner 2022-12-22 19:16:58 +0100
  • e60d14b Add readme by tmeissner 2022-12-22 19:15:19 +0100
  • b8d8b79 Initial commit by tmeissner 2022-12-22 19:08:01 +0100