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Increase pll clock to 10 MHz, add uart_loop design to readme

main
T. Meissner 2 years ago
parent
commit
32fa71a90b
7 changed files with 20 additions and 17 deletions
  1. +6
    -0
      README.md
  2. +6
    -9
      uart_loop/rtl/uart_loop.vhd
  3. +1
    -1
      uart_loop/sim/Makefile
  4. +1
    -1
      uart_loop/syn/Makefile
  5. +2
    -2
      uart_loop/syn/tb_uart_loop.v
  6. +3
    -3
      uart_reg/rtl/uart_reg.vhd
  7. +1
    -1
      uart_reg/syn/tb_uart_reg.v

+ 6
- 0
README.md View File

@ -8,6 +8,12 @@ Ongoing experiments with the Cologne Chip's GateMate FPGA architecture. All expe
Simple design which should display a blinking LED waving from LED1-LED8 of the GateMate FPGA Starter Kit. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA.
### uart_loop
Simple UART loop with UART RX & TX units and FIFO buffer between. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. With fifo depth >= 18 Yosys is infering *CC_BRAM_20K* instead of registers.
Beware: The simulation model of *CC_BRAM_20K* seems to be incorrect, so better set fifo depth < 18 or use yosys option `-nobram` when synthesizing the model for post-synthesis & post-implementation simulation.
### uart_reg
Register file which can be accessed through UART. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. It contains 8 registers storing values of one byte each. The first received byte on the axis in port contains command & address:


+ 6
- 9
uart_loop/rtl/uart_loop.vhd View File

@ -1,8 +1,5 @@
-- This design implements a register file which can
-- be accessed by an UART with 9600 baud
--
-- See into uart_ctrl.vhd for documentation of the protocol
-- used to read / write the register file.
-- Simple UART loop with UART RX & TX units and FIFO buffer
-- between. It's working at baudrate 9600.
library ieee ;
@ -44,7 +41,7 @@ begin
pll : CC_PLL
generic map (
REF_CLK => "10",
OUT_CLK => "1",
OUT_CLK => "10",
PERF_MD => "ECONOMY"
)
port map (
@ -68,7 +65,7 @@ begin
uart_rx : entity work.uart_rx
generic map (
CLK_DIV => 104
CLK_DIV => 1040
)
port map (
-- globals
@ -84,7 +81,7 @@ begin
axis_fifo : entity work.axis_fifo
generic map (
DEPTH => 64,
DEPTH => 16,
WIDTH => 8
)
port map (
@ -107,7 +104,7 @@ begin
uart_tx : entity work.uart_tx
generic map (
CLK_DIV => 104
CLK_DIV => 1040
)
port map (
-- globals


+ 1
- 1
uart_loop/sim/Makefile View File

@ -20,7 +20,7 @@ tb_${DESIGN_NAME}: ${LIB_SRC} ${RTL_SRC} ${SIM_SRC}
sim: tb_${DESIGN_NAME}
@echo "Run testbench ..."
ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error
ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error --wave=tb_${DESIGN_NAME}.ghw
work:
mkdir $@


+ 1
- 1
uart_loop/syn/Makefile View File

@ -2,7 +2,7 @@ DESIGN_NAME := uart_loop
WORK_FILES := ../../lib/user_components.vhd ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/${DESIGN_NAME}.vhd
GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8 -retime -nobram
YOSYSPIPE := -nomx8 -retime
# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
PNRFLAGS := -om 2
PNRTOOL := $(shell which p_r)


+ 2
- 2
uart_loop/syn/tb_uart_loop.v View File

@ -18,8 +18,8 @@ module CC_PLL #(
reg r_pll_clk;
reg r_user_pll_locked;
// OUT_FREQ = 1 MHz
integer clk_half_period = 500;
// OUT_FREQ = 10 MHz
integer clk_half_period = 50;
initial begin
r_pll_clk = 1'b0;


+ 3
- 3
uart_reg/rtl/uart_reg.vhd View File

@ -44,7 +44,7 @@ begin
pll : CC_PLL
generic map (
REF_CLK => "10",
OUT_CLK => "1",
OUT_CLK => "10",
PERF_MD => "ECONOMY"
)
port map (
@ -68,7 +68,7 @@ begin
uart_rx : entity work.uart_rx
generic map (
CLK_DIV => 104
CLK_DIV => 1040
)
port map (
-- globals
@ -99,7 +99,7 @@ begin
uart_tx : entity work.uart_tx
generic map (
CLK_DIV => 104
CLK_DIV => 1040
)
port map (
-- globals


+ 1
- 1
uart_reg/syn/tb_uart_reg.v View File

@ -19,7 +19,7 @@ module CC_PLL #(
reg r_user_pll_locked;
// OUT_FREQ = 1 MHz
integer clk_half_period = 500;
integer clk_half_period = 50;
initial begin
r_pll_clk = 1'b0;


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