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@ -1,6 +1,6 @@ |
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DESIGN_NAME := uart_reg |
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WORK_FILES := ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/uart_reg.vhd |
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GM_FILES := ../../lib/components.vhd |
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GM_FILES := ../../lib/rtl_components.vhd |
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GHDL_FLAGS := --std=08 --workdir=build -Pbuild |
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YOSYSPIPE := -nomx8 -luttree -retime |
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PNRFLAGS := -sp off -om 2 -cCP on |
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