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@ -36,14 +36,14 @@ begin |
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pll : CC_PLL |
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generic map ( |
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REF_CLK => "10", |
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OUT_CLK => "1", |
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PERF_MD => "SPEED" |
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OUT_CLK => "2", |
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PERF_MD => "ECONOMY" |
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) |
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port map ( |
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CLK_REF => clk_i, |
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CLK_FEEDBACK => '0', |
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USR_CLK_REF => '0', |
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USR_LOCKED_STDY_RST => not rst_n_i, |
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USR_LOCKED_STDY_RST => '0', |
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USR_PLL_LOCKED_STDY => open, |
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USR_PLL_LOCKED => s_pll_lock, |
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CLK270 => open, |
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@ -64,7 +64,7 @@ begin |
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begin |
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if (not s_rst_n) then |
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s_clk_cnt <= (others => '0'); |
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elsif (rising_edge(clk_i)) then |
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elsif (rising_edge(s_pll_clk)) then |
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s_clk_cnt <= s_clk_cnt + 1; |
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end if; |
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end process; |
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@ -74,10 +74,10 @@ begin |
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process (s_pll_clk, s_rst_n) is |
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begin |
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if (not s_rst_n) then |
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s_led <= (others => '0'); |
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elsif (rising_edge(clk_i)) then |
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s_led <= x"01"; |
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elsif (rising_edge(s_pll_clk)) then |
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if (s_clk_en) then |
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s_led <= s_led + 1; |
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s_led <= s_led(6 downto 0) & s_led(7); |
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end if; |
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end if; |
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end process; |
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