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Add make target to program FPGA

main
T. Meissner 2 years ago
parent
commit
a0fcc51dc8
1 changed files with 5 additions and 2 deletions
  1. +5
    -2
      blink/syn/Makefile

+ 5
- 2
blink/syn/Makefile View File

@ -3,10 +3,10 @@ WORK_FILES := ../rtl/blink.vhd
GM_FILES := ../../lib/components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8 -luttree -retime
PNRFLAGS := -sp off -om 3 -cdf off -pin off -plc off -cCP on
PNRFLAGS := -sp off -om 2 -cCP on
PNRTOOL := $(shell which p_r)
.PHONY: all syn imp
.PHONY: all syn imp prog
all: imp
syn: ${DESIGN_NAME}.v
@ -29,6 +29,9 @@ ${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
2>&1 | tee p_r-report.txt && \
mv ${DESIGN_NAME}*.bit ../$@
prog: ${DESIGN_NAME}.bit
openFPGALoader -b gatemate_evb_jtag $<
clean :
echo "# Cleaning files"
rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.bit

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