|
|
|
@ -1,8 +1,16 @@ |
|
|
|
# gatemate_experiments |
|
|
|
|
|
|
|
Ongoing experiments with the Cologne Chip's GateMate FPGA architecture. |
|
|
|
Ongoing experiments with the Cologne Chip's GateMate FPGA architecture. All experiments are done with teh GateMate FPGA Starter (Eval) Kit. |
|
|
|
|
|
|
|
## Designs |
|
|
|
|
|
|
|
### blink |
|
|
|
|
|
|
|
Simple design which should display incrementing binary numbers with LED1-LED8 of the GateMate FPGA Starter Kit. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. |
|
|
|
|
|
|
|
## Further Ressources |
|
|
|
|
|
|
|
* [GateMate FPGA](https://www.colognechip.com/programmable-logic/gatemate) |
|
|
|
* [GateMate FPGA Eval Board](https://www.colognechip.com/programmable-logic/gatemate-evaluation-board) |
|
|
|
* [GHDL VHDL Simulation & Synthesis](https://github.com/ghdl/ghdl) |
|
|
|
* [Yosys Synthesis Suite](https://github.com/YosysHQ/yosys) |
