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@ -26,6 +26,9 @@ architecture rtl of blink is |
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signal s_clk_cnt : unsigned(19 downto 0); |
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signal s_clk_en : boolean; |
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signal s_rst_n : std_logic; |
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signal s_cfg_end : std_logic; |
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signal s_led : unsigned(led_n_o'range); |
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begin |
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@ -33,14 +36,14 @@ begin |
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pll : CC_PLL |
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generic map ( |
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REF_CLK => "10", |
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OUT_CLK => "30", |
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OUT_CLK => "1", |
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PERF_MD => "SPEED" |
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) |
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port map ( |
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CLK_REF => clk_i, |
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CLK_FEEDBACK => '0', |
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USR_CLK_REF => '0', |
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USR_LOCKED_STDY_RST => '0', |
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USR_LOCKED_STDY_RST => not rst_n_i, |
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USR_PLL_LOCKED_STDY => open, |
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USR_PLL_LOCKED => s_pll_lock, |
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CLK270 => open, |
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@ -50,9 +53,16 @@ begin |
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CLK_REF_OUT => open |
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); |
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process (s_pll_clk, rst_n_i) is |
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cfg_end_inst : CC_CFG_END |
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port map ( |
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CFG_END => s_cfg_end |
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); |
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s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end; |
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process (s_pll_clk, s_rst_n) is |
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begin |
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if (not rst_n_i) then |
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if (not s_rst_n) then |
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s_clk_cnt <= (others => '0'); |
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elsif (rising_edge(clk_i)) then |
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s_clk_cnt <= s_clk_cnt + 1; |
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@ -61,9 +71,9 @@ begin |
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s_clk_en <= s_clk_cnt = (s_clk_cnt'range => '1'); |
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process (s_pll_clk, rst_n_i) is |
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process (s_pll_clk, s_rst_n) is |
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begin |
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if (not rst_n_i) then |
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if (not s_rst_n) then |
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s_led <= (others => '0'); |
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elsif (rising_edge(clk_i)) then |
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if (s_clk_en) then |
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