Use speed instead of moderate FPGA speed grade

blink/rtl/blink.vhd

@@ -43,7 +43,7 @@ begin
   generic map (
     REF_CLK => "10",
     OUT_CLK => "2",
-    PERF_MD => "ECONOMY"
+    PERF_MD => "SPEED"
   )
   port map (
     CLK_REF             => clk_i,

blink/syn/Makefile

@@ -4,7 +4,7 @@ GM_FILES    := ../../lib/rtl_components.vhd
 GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
 YOSYSPIPE   := -nomx8 -retime
 # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
-PNRFLAGS    := -om 2
+PNRFLAGS    := -om 3
 PNRTOOL     := $(shell which p_r)
 
 .PHONY: all syn imp prog syn_sim imp_sim

uart_loop/rtl/uart_loop.vhd

@@ -42,7 +42,7 @@ begin
   generic map (
     REF_CLK => "10",
     OUT_CLK => "10",
-    PERF_MD => "ECONOMY"
+    PERF_MD => "SPEED"
   )
   port map (
     CLK_REF             => clk_i,
@@ -81,7 +81,7 @@ begin
 
   axis_fifo : entity work.axis_fifo
   generic map (
-    DEPTH => 16,
+    DEPTH => 32,
     WIDTH => 8
   )
   port map (

uart_loop/syn/Makefile

@@ -4,7 +4,7 @@ GM_FILES    := ../../lib/rtl_components.vhd
 GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
 YOSYSPIPE   := -nomx8 -retime
 # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
-PNRFLAGS    := -om 2
+PNRFLAGS    := -om 3
 PNRTOOL     := $(shell which p_r)
 
 .PHONY: all syn imp prog syn_sim imp_sim

uart_reg/rtl/uart_reg.vhd

@@ -45,7 +45,7 @@ begin
   generic map (
     REF_CLK => "10",
     OUT_CLK => "10",
-    PERF_MD => "ECONOMY"
+    PERF_MD => "SPEED"
   )
   port map (
     CLK_REF             => clk_i,

uart_reg/syn/Makefile

@@ -4,7 +4,7 @@ GM_FILES    := ../../lib/rtl_components.vhd
 GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
 YOSYSPIPE   := -nomx8 -retime
 # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
-PNRFLAGS    := -om 2
+PNRFLAGS    := -om 3
 PNRTOOL     := $(shell which p_r)
 
 .PHONY: all syn imp prog syn_sim imp_sim

uart_trng/rtl/uart_trng.vhd

@@ -47,7 +47,7 @@ begin
   generic map (
     REF_CLK => "10",
     OUT_CLK => "10",
-    PERF_MD => "ECONOMY"
+    PERF_MD => "SPEED"
   )
   port map (
     CLK_REF             => clk_i,

uart_trng/syn/Makefile

@@ -4,7 +4,7 @@ GM_FILES    := ../../lib/rtl_components.vhd
 GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
 YOSYSPIPE   := -nomx8 -retime
 # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
-PNRFLAGS    := -om 2
+PNRFLAGS    := -om 3
 PNRTOOL     := $(shell which p_r)
 
 .PHONY: all syn imp prog syn_sim imp_sim