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gatemate_experiments
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Use speed instead of moderate FPGA speed grade

main
T. Meissner 3 years ago
parent
e845a0d530
commit
6b1b376932
8 changed files with 9 additions and 9 deletions
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  1. +1
    -1
      blink/rtl/blink.vhd
  2. +1
    -1
      blink/syn/Makefile
  3. +2
    -2
      uart_loop/rtl/uart_loop.vhd
  4. +1
    -1
      uart_loop/syn/Makefile
  5. +1
    -1
      uart_reg/rtl/uart_reg.vhd
  6. +1
    -1
      uart_reg/syn/Makefile
  7. +1
    -1
      uart_trng/rtl/uart_trng.vhd
  8. +1
    -1
      uart_trng/syn/Makefile

+ 1
- 1
blink/rtl/blink.vhd View File

@ -43,7 +43,7 @@ begin
generic map ( generic map (
REF_CLK => "10", REF_CLK => "10",
OUT_CLK => "2", OUT_CLK => "2",
PERF_MD => "ECONOMY"
PERF_MD => "SPEED"
) )
port map ( port map (
CLK_REF => clk_i, CLK_REF => clk_i,


+ 1
- 1
blink/syn/Makefile View File

@ -4,7 +4,7 @@ GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8 -retime YOSYSPIPE := -nomx8 -retime
# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
PNRFLAGS := -om 2
PNRFLAGS := -om 3
PNRTOOL := $(shell which p_r) PNRTOOL := $(shell which p_r)
.PHONY: all syn imp prog syn_sim imp_sim .PHONY: all syn imp prog syn_sim imp_sim


+ 2
- 2
uart_loop/rtl/uart_loop.vhd View File

@ -42,7 +42,7 @@ begin
generic map ( generic map (
REF_CLK => "10", REF_CLK => "10",
OUT_CLK => "10", OUT_CLK => "10",
PERF_MD => "ECONOMY"
PERF_MD => "SPEED"
) )
port map ( port map (
CLK_REF => clk_i, CLK_REF => clk_i,
@ -81,7 +81,7 @@ begin
axis_fifo : entity work.axis_fifo axis_fifo : entity work.axis_fifo
generic map ( generic map (
DEPTH => 16,
DEPTH => 32,
WIDTH => 8 WIDTH => 8
) )
port map ( port map (


+ 1
- 1
uart_loop/syn/Makefile View File

@ -4,7 +4,7 @@ GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8 -retime YOSYSPIPE := -nomx8 -retime
# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
PNRFLAGS := -om 2
PNRFLAGS := -om 3
PNRTOOL := $(shell which p_r) PNRTOOL := $(shell which p_r)
.PHONY: all syn imp prog syn_sim imp_sim .PHONY: all syn imp prog syn_sim imp_sim


+ 1
- 1
uart_reg/rtl/uart_reg.vhd View File

@ -45,7 +45,7 @@ begin
generic map ( generic map (
REF_CLK => "10", REF_CLK => "10",
OUT_CLK => "10", OUT_CLK => "10",
PERF_MD => "ECONOMY"
PERF_MD => "SPEED"
) )
port map ( port map (
CLK_REF => clk_i, CLK_REF => clk_i,


+ 1
- 1
uart_reg/syn/Makefile View File

@ -4,7 +4,7 @@ GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8 -retime YOSYSPIPE := -nomx8 -retime
# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
PNRFLAGS := -om 2
PNRFLAGS := -om 3
PNRTOOL := $(shell which p_r) PNRTOOL := $(shell which p_r)
.PHONY: all syn imp prog syn_sim imp_sim .PHONY: all syn imp prog syn_sim imp_sim


+ 1
- 1
uart_trng/rtl/uart_trng.vhd View File

@ -47,7 +47,7 @@ begin
generic map ( generic map (
REF_CLK => "10", REF_CLK => "10",
OUT_CLK => "10", OUT_CLK => "10",
PERF_MD => "ECONOMY"
PERF_MD => "SPEED"
) )
port map ( port map (
CLK_REF => clk_i, CLK_REF => clk_i,


+ 1
- 1
uart_trng/syn/Makefile View File

@ -4,7 +4,7 @@ GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8 -retime YOSYSPIPE := -nomx8 -retime
# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate?
PNRFLAGS := -om 2
PNRFLAGS := -om 3
PNRTOOL := $(shell which p_r) PNRTOOL := $(shell which p_r)
.PHONY: all syn imp prog syn_sim imp_sim .PHONY: all syn imp prog syn_sim imp_sim


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