tmeissner
/
gatemate_experiments
1
0
Fork 0
Code Issues 0 Pull Requests 0 Projects 0 Releases 0 Wiki Activity
Browse Source

Update top-level & Makefile to use new AES CF module

main
T. Meissner 1 year ago
parent
70f13efdb2
commit
dc0e1aa90f
3 changed files with 55 additions and 41 deletions
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. +37
    -24
      neorv32_aes/rtl/neorv32_aes.vhd
  2. +7
    -6
      neorv32_aes/syn/Makefile
  3. +11
    -11
      neorv32_aes/syn/neorv32_aes.ccf

+ 37
- 24
neorv32_aes/rtl/neorv32_aes.vhd View File

@ -36,6 +36,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neorv32;
use neorv32.neorv32_package.all;
library gatemate;
use gatemate.components.all;
@ -46,17 +49,18 @@ entity neorv32_aes is
clk_i : in std_logic; -- 10 MHz clock
rst_n_i : in std_logic; -- SW3 button
-- LED outputs
led_n_o : out std_logic_vector(7 downto 0);
led_n_o : out std_logic_vector(7 downto 0)
-- UART0
uart_rx_i : in std_logic; -- PMODA IO
uart_tx_o : out std_logic -- PMODA IO
-- uart_rx_i : in std_logic; -- PMODA IO
-- uart_tx_o : out std_logic -- PMODA IO
);
end entity;
architecture rtl of neorv32_aes is
-- configuration --
constant f_clock_c : natural := 20_000_000; -- clock frequency in Hz
constant f_clock_c : natural := 10_000_000; -- clock frequency in Hz
-- Globals
signal s_pll_lock : std_logic;
@ -65,14 +69,14 @@ architecture rtl of neorv32_aes is
signal s_rst_n : std_logic;
signal s_con_gpio : std_logic_vector(3 downto 0);
signal s_con_gpio : std_ulogic_vector(63 downto 0);
begin
PLL : CC_PLL
generic map (
REF_CLK => "10",
OUT_CLK => "20",
OUT_CLK => "10",
PERF_MD => "SPEED"
)
port map (
@ -98,18 +102,30 @@ begin
-- The core of the problem ----------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_inst: entity work.neorv32_top
neorv32_inst: entity neorv32.neorv32_top
generic map (
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz
CPU_EXTENSION_RISCV_M => true,
FAST_MUL_EN => false,
FAST_SHIFT_EN => false,
MEM_INT_IMEM_SIZE => 8*1024,
MEM_INT_DMEM_SIZE => 16*1024,
IO_MTIME_EN => false,
IO_WDT_EN => false,
IO_TRNG_EN => false,
IO_CFS_EN => true
CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz
INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM
-- RISC-V CPU Extensions --
CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
CPU_EXTENSION_RISCV_M => true, -- implement mul/div extension?
CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?
CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters?
-- Tuning Options --
FAST_MUL_EN => false,
FAST_SHIFT_EN => false,
-- Internal Instruction memory --
MEM_INT_IMEM_EN => true, -- implement processor-internal instruction memory
MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes
-- Internal Data memory --
MEM_INT_DMEM_EN => true, -- implement processor-internal data memory
MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
-- Processor peripherals --
IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
IO_UART0_EN => false, -- implement primary universal asynchronous receiver/transmitter (UART0)?
IO_CFS_EN => false, -- implement custom functions subsystem (CFS)?
IO_AES_EN => true -- implement AES(128) custom function?
)
port map (
-- Global control --
@ -118,21 +134,18 @@ begin
-- GPIO
gpio_o => s_con_gpio,
-- primary UART0
uart_txd_o => uart_tx_o,
uart_rxd_i => uart_rx_i
uart0_txd_o => open,
uart0_rxd_i => '0'
);
-- p_r ERROR when connecting uart_rx_i & yosys option -retime (with both Yosys inferred & instantiated CC_BRAM_40K or CC_BRAM_40K memory)
-- FATAL ERROR: RAM 4070 Output DOA[6] not used but Input DIA[6] used!
-- program finished with exit code: 2
-- p_r ERROR with FAST_MUL_EN (even with the suggested p_r option sitched off)
-- p_r ERROR with FAST_MUL_EN (fix with suggested p_r option switched off)
-- FATAL ERROR: CP-lines in Multiplier cannot be used for CLK; please switch off using CP-lines for CLK (-cCP)
-- IO Connection --------------------------------------------------------------------------
-- -------------------------------------------------------------------------------------------
led_n_o(3 downto 0) <= s_con_gpio;
led_n_o(7 downto 4) <= (others => '1');
-- uart_tx_o <= uart_rx_i;
led_n_o <= not std_logic_vector(s_con_gpio(7 downto 0));
end architecture;

+ 7
- 6
neorv32_aes/syn/Makefile View File

@ -18,7 +18,6 @@ NEORV32_CORE_SRC := \
$(NEORV32_CORE_DIR)/neorv32_boot_rom.vhd \
$(NEORV32_CORE_DIR)/neorv32_bus_keeper.vhd \
$(NEORV32_CORE_DIR)/neorv32_busswitch.vhd \
$(NEORV32_CORE_DIR)/neorv32_cfs.vhd \
$(NEORV32_CORE_DIR)/neorv32_cpu.vhd \
$(NEORV32_CORE_DIR)/neorv32_cpu_alu.vhd \
$(NEORV32_CORE_DIR)/neorv32_cpu_bus.vhd \
@ -43,25 +42,27 @@ NEORV32_CORE_SRC := \
$(NEORV32_CORE_DIR)/neorv32_slink.vhd \
$(NEORV32_CORE_DIR)/neorv32_spi.vhd \
$(NEORV32_CORE_DIR)/neorv32_sysinfo.vhd \
$(NEORV32_CORE_DIR)/neorv32_top.vhd \
$(NEORV32_CORE_DIR)/neorv32_trng.vhd \
$(NEORV32_CORE_DIR)/neorv32_twi.vhd \
$(NEORV32_CORE_DIR)/neorv32_uart.vhd \
$(NEORV32_CORE_DIR)/neorv32_wdt.vhd \
$(NEORV32_CORE_DIR)/neorv32_wishbone.vhd \
$(NEORV32_CORE_DIR)/neorv32_xip.vhd \
$(NEORV32_CORE_DIR)/neorv32_xirq.vhd
$(NEORV32_CORE_DIR)/neorv32_xirq.vhd \
$(NEORV32_CORE_DIR)/neorv32_cfs.vhd \
$(NEORV32_CORE_DIR)/neorv32_cfs_aes.vhd \
$(NEORV32_CORE_DIR)/neorv32_top.vhd
NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} \
${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC}
WORK_FILES := ../rtl/neorv32_ProcessorTop_MinimalUart.vhd ../rtl/${DESIGN_NAME}.vhd
WORK_FILES := ../rtl/${DESIGN_NAME}.vhd
GM_FILES := ../../lib/rtl_components.vhd
GHDL_FLAGS := --std=08 --workdir=build -Pbuild
YOSYSPIPE := -nomx8
# -retime -cCP off
PNRFLAGS := -om 3
# -retime
PNRFLAGS := -om 3 -cCP on
PNRTOOL := $(shell which p_r)
.PHONY: all syn imp prog syn_sim imp_sim


+ 11
- 11
neorv32_aes/syn/neorv32_aes.ccf View File

@ -12,14 +12,14 @@ Pin_out "led_n_o[5]" Loc = "IO_EB_B6"; # LED D6
Pin_out "led_n_o[6]" Loc = "IO_EB_B7"; # LED D7
Pin_out "led_n_o[7]" Loc = "IO_EB_B8"; # LED D8
Pin_in "uart_rx_i" Loc = "IO_NB_A1"; # PMODA IO3
Pin_out "uart_tx_o" Loc = "IO_NB_A0"; # PMODA IO1
Pin_out "debug_o[0]" Loc = "IO_NB_A4";
Pin_out "debug_o[1]" Loc = "IO_NB_A5";
Pin_out "debug_o[2]" Loc = "IO_NB_A6";
Pin_out "debug_o[3]" Loc = "IO_NB_A7";
Pin_out "debug_o[4]" Loc = "IO_NB_B4";
Pin_out "debug_o[5]" Loc = "IO_NB_B5";
Pin_out "debug_o[6]" Loc = "IO_NB_B6";
Pin_out "debug_o[7]" Loc = "IO_NB_B7";
#Pin_in "uart_rx_i" Loc = "IO_NB_A1"; # PMODA IO3
#Pin_out "uart_tx_o" Loc = "IO_NB_A0"; # PMODA IO1
#
#Pin_out "debug_o[0]" Loc = "IO_NB_A4";
#Pin_out "debug_o[1]" Loc = "IO_NB_A5";
#Pin_out "debug_o[2]" Loc = "IO_NB_A6";
#Pin_out "debug_o[3]" Loc = "IO_NB_A7";
#Pin_out "debug_o[4]" Loc = "IO_NB_B4";
#Pin_out "debug_o[5]" Loc = "IO_NB_B5";
#Pin_out "debug_o[6]" Loc = "IO_NB_B6";
#Pin_out "debug_o[7]" Loc = "IO_NB_B7";

Write Preview
Loading…
Cancel
Save