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@ -19,9 +19,9 @@ port ( |
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USR_LOCKED_STDY_RST : in std_logic; |
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USR_PLL_LOCKED_STDY : out std_logic; |
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USR_PLL_LOCKED : out std_logic; |
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CLK270 : out std_logic; |
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CLK180 : out std_logic; |
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CLK0 : out std_logic := '1'; |
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CLK270 : out std_logic := '0'; |
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CLK180 : out std_logic := '0'; |
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CLK0 : out std_logic := '0'; |
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CLK90 : out std_logic := '0'; |
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CLK_REF_OUT : out std_logic |
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); |
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@ -30,23 +30,27 @@ end entity; |
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architecture sim of CC_PLL is |
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constant c_period_ns : real := (1000.0 / real'value(OUT_CLK)); |
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constant c_half_period_ns : real := c_period_ns / 2.0; |
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signal s_pll_clk_2 : std_logic := '1'; |
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signal s_pll_clk_pos : std_logic := '0'; |
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signal s_pll_clk_neg : std_logic := '0'; |
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begin |
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Log : process is |
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begin |
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report CC_PLL'instance_name & " CC_PLL CLK0 = " & to_string(1000.0/(c_period_ns), 2) & " MHz"; |
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wait; |
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end process; |
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CLK0 <= not CLK0 after c_half_period_ns * ns; |
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CLK90 <= transport CLK0 after (c_half_period_ns / 2.0) * ns; |
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CLK180 <= not CLK0; |
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CLK270 <= not CLK90; |
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CLK_REF_OUT <= CLK_REF; |
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-- First create a clock with freq = 2 * OUT_CLK; |
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s_pll_clk_2 <= not s_pll_clk_2 after (250.0 / real'value(OUT_CLK)) * ns; |
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-- Then create clocks with freq = OUT_CLK and shifted by 180 degree |
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s_pll_clk_pos <= not s_pll_clk_pos when rising_edge(s_pll_clk_2); |
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s_pll_clk_neg <= not s_pll_clk_pos when falling_edge(s_pll_clk_2); |
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-- Finally assign the clock outputs to avoid delta cycle delay problems |
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-- All these clocks should by phase aligned |
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CLK0 <= s_pll_clk_pos; |
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CLK90 <= s_pll_clk_neg; |
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CLK180 <= not s_pll_clk_pos; |
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CLK270 <= not s_pll_clk_neg; |
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CLK_REF_OUT <= CLK_REF or USR_CLK_REF; |
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USR_PLL_LOCKED <= '1'; |
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