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T. Meissner a3cabb7747 Refactoring of CC_PLL simulation model 2 years ago
blink Add user_components.vhd containing generic RTL modules 2 years ago
lib Refactoring of CC_PLL simulation model 2 years ago
uart_reg Rename components.vhd to rtl_components.vhd 2 years ago
LICENSE.md Add license 2 years ago
README.md Add blink design info and more links to README 2 years ago

README.md

gatemate_experiments

Ongoing experiments with the Cologne Chip's GateMate FPGA architecture. All experiments are done with teh GateMate FPGA Starter (Eval) Kit.

Designs

Simple design which should display incrementing binary numbers with LED1-LED8 of the GateMate FPGA Starter Kit. It uses CC_PLL & CC_CFG_END primitives of the GateMate FPGA.

Further Ressources