T. Meissner
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a3cabb7747
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Refactoring of CC_PLL simulation model
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2 years ago |
T. Meissner
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3b6a315a0d
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Add user_components.vhd containing generic RTL modules
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2 years ago |
T. Meissner
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6cffeef4a5
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Rename components.vhd to rtl_components.vhd
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2 years ago |
T. Meissner
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61affc8b49
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Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations
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2 years ago |
T. Meissner
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0e84416a92
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Rename uart folder to uart_reg
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2 years ago |
T. Meissner
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1003634110
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Add inital version of uart register test design
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2 years ago |
T. Meissner
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cfa6f88c55
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Add simple gatemate primitives simulation components
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2 years ago |
T. Meissner
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012de1f868
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RTL refactoring
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2 years ago |
T. Meissner
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d57f683506
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Adapt sim to updated RTL
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2 years ago |
T. Meissner
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133e25aa3d
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Let LEDs rotate instead of counting up
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2 years ago |
T. Meissner
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a0fcc51dc8
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Add make target to program FPGA
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2 years ago |
T. Meissner
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eb0d52e2d6
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Add blink design info and more links to README
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2 years ago |
T. Meissner
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81be6cfd05
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Add CC_CFG_END unit, Use PLL lock & cfg_end for reset
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2 years ago |
T. Meissner
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f28d35d12b
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Also remove bit file in clean target
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2 years ago |
T. Meissner
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efaca0c912
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Add PnR pass and constraint file
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2 years ago |
T. Meissner
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95887cb31d
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Add PLL to blink design
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2 years ago |
T. Meissner
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45ced01c22
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Add blink design & simulation
* blink should display incrementing binary numbers
at LED1-LED8 of the GateMate FPGA Starter Kit.
* Increment is done with circa 9.5 Hz
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2 years ago |
T. Meissner
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a38eedb326
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Add license
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2 years ago |
T. Meissner
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eea3893d1c
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Fix readme
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2 years ago |
T. Meissner
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e60d14ba47
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Add readme
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2 years ago |
T. Meissner
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b8d8b791dc
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Initial commit
* Add VHDL component library for Gatemate FPGA primitives
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2 years ago |