Add VHDL sim for RTL & Verilog sim for post-syn simulation

neorv32_aes/sim/Makefile

@@ -0,0 +1,108 @@
+DESIGN_NAME := neorv32_aes
+
+NEORV32_CORE_DIR  := ../../neorv32/rtl/core
+NEORV32_PKG       := $(NEORV32_CORE_DIR)/neorv32_package.vhd
+NEORV32_APP_SRC   := $(NEORV32_CORE_DIR)/neorv32_application_image.vhd
+NEORV32_TEMPLATES := ../../neorv32/rtl/processor_templates
+
+NEORV32_MEM_ENTITIES := \
+  $(NEORV32_CORE_DIR)/neorv32_dmem.entity.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_imem.entity.vhd
+
+NEORV32_MEM_SRC := \
+  $(NEORV32_CORE_DIR)/mem/neorv32_imem.default.vhd \
+  $(NEORV32_CORE_DIR)/mem/neorv32_dmem.default.vhd
+
+NEORV32_CORE_SRC := \
+  $(NEORV32_CORE_DIR)/neorv32_bootloader_image.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_boot_rom.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_bus_keeper.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_busswitch.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_alu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_bus.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_control.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_bitmanip.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_cfu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_fpu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_muldiv.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_shifter.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_decompressor.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_regfile.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_debug_dm.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_debug_dtm.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_fifo.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_gpio.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_gptmr.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_icache.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_mtime.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_neoled.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_onewire.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_pwm.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_slink.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_spi.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_sysinfo.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_trng.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_twi.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_uart.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_wdt.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_wishbone.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_xip.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_xirq.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cfs.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cfs_aes.vhd \
+  ../rtl/neorv32_top.vhd
+
+NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} \
+  ${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC}
+
+AES_DIR   := ../../cryptocores/aes/rtl/vhdl
+CRYPTO_SRC := \
+  $(AES_DIR)/aes_pkg.vhd \
+  $(AES_DIR)/aes_enc.vhd \
+  $(AES_DIR)/aes_dec.vhd \
+  $(AES_DIR)/aes.vhd \
+  $(AES_DIR)/../../../ctraes/rtl/vhdl/ctraes.vhd
+
+
+WORK_FILES   := ../rtl/${DESIGN_NAME}.vhd tb_${DESIGN_NAME}.vhd
+GM_FILES     := ../../lib/rtl_components.vhd ../../lib/sim_components.vhd
+
+SIM_FLAGS   := --std=08 -fpsl --workdir=work -Pwork
+
+.PHONY: all compile sim clean
+
+all: sim
+compile: tb_${DESIGN_NAME}
+
+
+work/work-obj08.cf: ${WORK_FILES} work/gatemate-obj08.cf work/neorv32-obj08.cf
+	mkdir -p work
+	ghdl -a ${SIM_FLAGS} --work=work ${WORK_FILES}
+
+work/neorv32-obj08.cf: work/gatemate-obj08.cf work/cryptocores-obj08.cf ${NEORV32_SRC}
+	mkdir -p work
+	ghdl -a $(SIM_FLAGS) --work=neorv32 ${NEORV32_SRC}
+
+work/cryptocores-obj08.cf: ${CRYPTO_SRC}
+	mkdir -p work
+	ghdl -a $(SIM_FLAGS) --work=cryptocores ${CRYPTO_SRC}
+
+work/gatemate-obj08.cf: ${GM_FILES}
+	mkdir -p work
+	ghdl -a ${SIM_FLAGS} --work=gatemate ${GM_FILES}
+
+tb_${DESIGN_NAME}: work/gatemate-obj08.cf work/cryptocores-obj08.cf work/neorv32-obj08.cf work/work-obj08.cf
+	@echo "Elaborate testbench & design ..."
+	ghdl -e ${SIM_FLAGS} -Pwork $@
+
+sim: tb_${DESIGN_NAME}
+	@echo "Run testbench ..."
+	ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error --ieee-asserts=disable --wave=tb_${DESIGN_NAME}.ghw
+
+work:
+	mkdir $@
+
+clean:
+	@echo "Cleaning simulation files ..."
+	rm -rf tb_${DESIGN_NAME} tb_${DESIGN_NAME}.ghw *.o work/

neorv32_aes/sim/tb_neorv32_aes.vhd

@@ -0,0 +1,73 @@
+library ieee ;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.env.all;
+
+
+entity tb_neorv32_aes is
+end entity tb_neorv32_aes;
+
+
+architecture sim of tb_neorv32_aes is
+
+  constant c_baudrate  : natural := 9600;
+  constant c_period_ns : time := 1000000000 / c_baudrate * ns;
+
+  procedure uart_send (       data : in std_logic_vector(7 downto 0);
+                       signal   tx : out std_logic) is
+  begin
+    report "UART send: 0x" & to_hstring(data);
+    tx <= '0';
+    wait for c_period_ns;
+    for i in 0 to 7 loop
+      tx <= data(i);
+      wait for c_period_ns;
+    end loop;
+    tx <= '1';
+    wait for c_period_ns;
+  end procedure;
+
+  procedure uart_recv (       data : out std_logic_vector(7 downto 0);
+                       signal   rx : in  std_logic) is
+  begin
+    wait until not rx;
+    wait for c_period_ns;   -- Skip start bit
+    wait for c_period_ns/2;
+    for i in 0 to 7 loop
+      data(i) := rx;
+      wait for c_period_ns;
+    end loop;
+    report "UART recv: 0x" & to_hstring(data);
+  end procedure;
+
+  signal s_clk   : std_logic := '1';
+  signal s_rst_n : std_logic := '0';
+
+  signal s_len_n : std_logic_vector(7 downto 0);
+  signal s_debug : std_logic_vector(15 downto 0);
+
+begin
+
+  dut : entity work.neorv32_aes
+  port map (
+    clk_i     => s_clk,
+    rst_n_i   => s_rst_n,
+    --
+    led_n_o => s_len_n,
+    --uart_tx_o => s_uart_tx
+    --uart_rx_i => s_uart_rx
+    debug_o => s_debug
+  );
+
+  s_rst_n <= '1' after 120 ns;
+  s_clk   <= not s_clk after 50 ns;
+
+  process is
+  begin
+    wait for 2 ms;
+    stop(0);
+  end process;
+
+
+end architecture;

neorv32_aes/syn/tb_neorv32_aes.v

@@ -0,0 +1,102 @@
+`timescale 1 ns/10 ps  // time-unit = 1 ns, precision = 10 ps
+
+`define USE_RAM
+
+// simplified CC_PLL model
+module CC_PLL #(
+  parameter REF_CLK = "", // e.g. "10.0"
+  parameter OUT_CLK = "", // e.g. "50.0"
+  parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
+  parameter LOW_JITTER = 1,
+  parameter CI_FILTER_CONST = 2,
+  parameter CP_FILTER_CONST = 4
+)(
+  input  CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
+  input  USR_LOCKED_STDY_RST, USR_SET_SEL,
+  output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
+  output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
+);
+
+  reg r_pll_clk;
+  reg r_user_pll_locked;
+
+  // OUT_FREQ = 10 MHz
+  localparam clk_half_period = 50;
+
+  initial begin
+    r_pll_clk         = 1'b0;
+    r_user_pll_locked = 1'b1;
+  end
+
+  always #clk_half_period r_pll_clk = ~r_pll_clk;
+
+  assign CLK0 = r_pll_clk;
+  assign USR_PLL_LOCKED = r_user_pll_locked;
+
+endmodule
+
+
+// simplified CC_CFG_END model
+module CC_CFG_END (
+  output CFG_END
+);
+
+  assign CFG_END = 1'b1;
+
+endmodule
+
+module tb_neorv32_aes;
+
+  // DUT in/out
+  reg  clk   = 1'b0;
+  reg  rst_n = 1'b1;
+  wire [7:0]  led;
+  wire [63:0] debug;
+  reg uart_rx;
+  wire uart_tx;
+
+  // Testbench variables
+
+  // Testbench 1/2 clock period
+  localparam clk_half_period = 50;
+
+  // UART period calculation (9600 baud)
+  localparam uart_bit_period = 1000000000 / 9600;
+  localparam uart_bit_half_period = uart_bit_period/2;
+
+  neorv32_aes UUT (.clk_i(clk), .rst_n_i(rst_n), .led_n_o(led), .debug_o(debug));
+//  neorv32_aes UUT (.clk_i(clk), .rst_n_i(rst_n), .led_n_o(led), .uart_tx_o(uart_tx), .uart_rx_i(uart_rx));
+
+  // set dumpfile
+  initial begin
+    $dumpfile ("tb_neorv32_aes.fst");
+    $dumpvars (0, tb_neorv32_aes);
+  end
+    
+  // Setup simulation
+  initial begin
+    uart_rx = 1'b1;
+    #1   rst_n = 1'b0;
+    #120 rst_n = 1'b1;
+  end
+
+  // Generate 10 mhz clock
+  always #clk_half_period clk = !clk;
+
+  // Stimuli generator
+  initial 
+    forever @(posedge rst_n) begin
+    // Simulate for 100 us
+    #500_000
+//    @(negedge led[0]);
+//    #100
+    $display ("NEORV32 test finished");
+    $finish;
+  end
+
+  // Monitor
+  initial begin
+    $monitor("monitor time=%t ns, rst_n=%b, led=%b, imem.addr=%d, dmem.addr=%h", $time, rst_n, led, debug[31:2], debug[63:32]);
+  end
+
+endmodule