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+259 -0neorv32_aes/rtl/neorv32_ProcessorTop_MinimalUart.vhd
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+29 -10neorv32_aes/rtl/neorv32_aes.vhd
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neorv32_aes/rtl/neorv32_ProcessorTop_MinimalUart.vhd
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| @ -0,0 +1,259 @@ | |||
| -- ################################################################################################# | |||
| -- # << NEORV32 - Minimal setup without a bootloader bur UART0 enabled >> # | |||
| -- # ********************************************************************************************* # | |||
| -- # BSD 3-Clause License # | |||
| -- # # | |||
| -- # Copyright (c) 2022, Torsten Meissner. All rights reserved. # | |||
| -- # # | |||
| -- # Redistribution and use in source and binary forms, with or without modification, are # | |||
| -- # permitted provided that the following conditions are met: # | |||
| -- # # | |||
| -- # 1. Redistributions of source code must retain the above copyright notice, this list of # | |||
| -- # conditions and the following disclaimer. # | |||
| -- # # | |||
| -- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # | |||
| -- # conditions and the following disclaimer in the documentation and/or other materials # | |||
| -- # provided with the distribution. # | |||
| -- # # | |||
| -- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # | |||
| -- # endorse or promote products derived from this software without specific prior written # | |||
| -- # permission. # | |||
| -- # # | |||
| -- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # | |||
| -- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # | |||
| -- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # | |||
| -- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # | |||
| -- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # | |||
| -- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # | |||
| -- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # | |||
| -- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # | |||
| -- # OF THE POSSIBILITY OF SUCH DAMAGE. # | |||
| -- # ********************************************************************************************* # | |||
| -- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # | |||
| -- ################################################################################################# | |||
| library ieee; | |||
| use ieee.std_logic_1164.all; | |||
| use ieee.numeric_std.all; | |||
| library neorv32; | |||
| entity neorv32_top is | |||
| generic ( | |||
| CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz | |||
| HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) | |||
| -- RISC-V CPU Extensions -- | |||
| CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? | |||
| CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? | |||
| CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? | |||
| CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? | |||
| CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) | |||
| CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? | |||
| CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? | |||
| -- Extension Options -- | |||
| FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier | |||
| FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations | |||
| -- Physical Memory Protection (PMP) -- | |||
| PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16) | |||
| PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes | |||
| -- Hardware Performance Monitors (HPM) -- | |||
| HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) | |||
| HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) | |||
| -- Internal Instruction memory -- | |||
| MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory | |||
| MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes | |||
| -- Internal Data memory -- | |||
| MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory | |||
| MEM_INT_DMEM_SIZE : natural := 64*1024; -- size of processor-internal data memory in bytes | |||
| -- Internal Cache memory -- | |||
| ICACHE_EN : boolean := false; -- implement instruction cache | |||
| ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 | |||
| ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 | |||
| ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 | |||
| -- Processor peripherals -- | |||
| IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? | |||
| IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? | |||
| IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? | |||
| IO_PWM_NUM_CH : natural := 3; -- number of PWM channels to implement (0..60); 0 = disabled | |||
| IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? | |||
| IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)? | |||
| IO_CFS_EN : boolean := true -- implement custom functions subsystem (CFS)? | |||
| ); | |||
| port ( | |||
| clk_i : in std_logic; | |||
| rstn_i : in std_logic; | |||
| -- GPIO (available if IO_GPIO_EN = true) -- | |||
| gpio_o : out std_ulogic_vector(3 downto 0); | |||
| -- primary UART0 (available if IO_UART0_EN = true) -- | |||
| uart_txd_o : out std_ulogic; -- UART0 send data | |||
| uart_rxd_i : in std_ulogic := '0' -- UART0 receive data | |||
| ); | |||
| end entity; | |||
| architecture rtl of neorv32_top is | |||
| -- internal IO connection -- | |||
| signal con_gpio_o : std_ulogic_vector(63 downto 0); | |||
| signal con_pwm_o : std_ulogic_vector(59 downto 0); | |||
| begin | |||
| -- IO Connection -------------------------------------------------------------------------- | |||
| -- ------------------------------------------------------------------------------------------- | |||
| -- GPIO -- | |||
| gpio_o <= con_gpio_o(3 downto 0); | |||
| -- The core of the problem ---------------------------------------------------------------- | |||
| -- ------------------------------------------------------------------------------------------- | |||
| neorv32_inst: entity neorv32.neorv32_top | |||
| generic map ( | |||
| -- General -- | |||
| CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz | |||
| INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM | |||
| HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (32-bit) | |||
| -- On-Chip Debugger (OCD) -- | |||
| ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger? | |||
| -- RISC-V CPU Extensions -- | |||
| CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? | |||
| CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? | |||
| CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? | |||
| CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? | |||
| CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT regs!) | |||
| CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? | |||
| CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? | |||
| CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? | |||
| -- Extension Options -- | |||
| FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier | |||
| FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations | |||
| -- Physical Memory Protection (PMP) -- | |||
| PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16) | |||
| PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes | |||
| -- Hardware Performance Monitors (HPM) -- | |||
| HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) | |||
| HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (1..64) | |||
| -- Internal Instruction memory -- | |||
| MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory | |||
| MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes | |||
| -- Internal Data memory -- | |||
| MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory | |||
| MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes | |||
| -- Internal Cache memory -- | |||
| ICACHE_EN => ICACHE_EN, -- implement instruction cache | |||
| ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 | |||
| ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 | |||
| ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 | |||
| -- External memory interface -- | |||
| MEM_EXT_EN => false, -- implement external memory bus interface? | |||
| MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) | |||
| -- Processor peripherals -- | |||
| IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? | |||
| IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? | |||
| IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? | |||
| IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? | |||
| IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? | |||
| IO_TWI_EN => false, -- implement two-wire interface (TWI)? | |||
| IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled | |||
| IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? | |||
| IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? | |||
| IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? | |||
| IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic | |||
| IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits | |||
| IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits | |||
| IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? | |||
| ) | |||
| port map ( | |||
| -- Global control -- | |||
| clk_i => clk_i, -- global clock, rising edge | |||
| rstn_i => rstn_i, -- global reset, low-active, async | |||
| -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- | |||
| jtag_trst_i => '0', -- low-active TAP reset (optional) | |||
| jtag_tck_i => '0', -- serial clock | |||
| jtag_tdi_i => '0', -- serial data input | |||
| jtag_tdo_o => open, -- serial data output | |||
| jtag_tms_i => '0', -- mode select | |||
| -- Wishbone bus interface (available if MEM_EXT_EN = true) -- | |||
| wb_tag_o => open, -- request tag | |||
| wb_adr_o => open, -- address | |||
| wb_dat_i => (others => '0'), -- read data | |||
| wb_dat_o => open, -- write data | |||
| wb_we_o => open, -- read/write | |||
| wb_sel_o => open, -- byte enable | |||
| wb_stb_o => open, -- strobe | |||
| wb_cyc_o => open, -- valid cycle | |||
| wb_ack_i => '0', -- transfer acknowledge | |||
| wb_err_i => '0', -- transfer error | |||
| -- Advanced memory control signals (available if MEM_EXT_EN = true) -- | |||
| fence_o => open, -- indicates an executed FENCE operation | |||
| fencei_o => open, -- indicates an executed FENCEI operation | |||
| -- GPIO (available if IO_GPIO_EN = true) -- | |||
| gpio_o => con_gpio_o, -- parallel output | |||
| gpio_i => (others => '0'), -- parallel input | |||
| -- primary UART0 (available if IO_UART0_EN = true) -- | |||
| uart0_txd_o => uart_txd_o, -- UART0 send data | |||
| uart0_rxd_i => uart_rxd_i, -- UART0 receive data | |||
| uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional | |||
| uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional | |||
| -- secondary UART1 (available if IO_UART1_EN = true) -- | |||
| uart1_txd_o => open, -- UART1 send data | |||
| uart1_rxd_i => '0', -- UART1 receive data | |||
| uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional | |||
| uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional | |||
| -- SPI (available if IO_SPI_EN = true) -- | |||
| spi_sck_o => open, -- SPI serial clock | |||
| spi_sdo_o => open, -- controller data out, peripheral data in | |||
| spi_sdi_i => '0', -- controller data in, peripheral data out | |||
| spi_csn_o => open, -- SPI CS | |||
| -- TWI (available if IO_TWI_EN = true) -- | |||
| twi_sda_io => open, -- twi serial data line | |||
| twi_scl_io => open, -- twi serial clock line | |||
| -- PWM (available if IO_PWM_NUM_CH > 0) -- | |||
| pwm_o => open, -- pwm channels | |||
| -- Custom Functions Subsystem IO -- | |||
| cfs_in_i => (others => '0'), -- custom CFS inputs conduit | |||
| cfs_out_o => open, -- custom CFS outputs conduit | |||
| -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- | |||
| neoled_o => open, -- async serial data line | |||
| -- System time -- | |||
| mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) | |||
| mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) | |||
| -- Interrupts -- | |||
| mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false | |||
| msw_irq_i => '0', -- machine software interrupt | |||
| mext_irq_i => '0' -- machine external interrupt | |||
| ); | |||
| end architecture; | |||