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@ -43,13 +43,12 @@ module CC_CFG_END ( |
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endmodule |
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module tb_uart_reg; |
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module tb_uart_trng; |
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// DUT in/out |
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reg clk = 1'b0; |
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reg rst_n = 1'b1; |
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reg uart_rx; |
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wire uart_tx; |
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reg uart_tx; |
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// Testbench variables |
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reg [7:0] tx_data = 8'h0; |
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@ -62,17 +61,16 @@ module tb_uart_reg; |
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localparam uart_bit_period = 1000000000 / 9600; |
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localparam uart_bit_half_period = uart_bit_period/2; |
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uart_reg UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_rx_i(uart_rx), .uart_tx_o(uart_tx)); |
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uart_trng UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_tx_o(uart_tx)); |
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// set dumpfile |
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initial begin |
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$dumpfile ("tb_uart_reg.fst"); |
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$dumpvars (0, tb_uart_reg); |
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$dumpfile ("tb_uart_trng.fst"); |
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$dumpvars (0, tb_uart_trng); |
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end |
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// Setup simulation |
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initial begin |
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uart_rx = 1'b1; |
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#1 rst_n = 1'b0; |
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#120 rst_n = 1'b1; |
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end |
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@ -80,27 +78,6 @@ module tb_uart_reg; |
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// Generate 10 mhz clock |
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always #clk_half_period clk = !clk; |
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// Stimuli generator |
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initial |
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forever @(posedge rst_n) begin |
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uart_rx = 1'b1; |
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#uart_bit_period; |
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for (integer tx = 0; tx < 32; tx = tx + 1) begin |
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tx_data = tx; |
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$display ("UART send: 0x%h", tx_data); |
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uart_rx = 1'b0; |
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#uart_bit_period; |
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for (integer i = 0; i < 7; i = i + 1) begin |
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uart_rx = tx_data[i]; |
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#uart_bit_period; |
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end |
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uart_rx = 1'b1; |
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#uart_bit_period; |
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#uart_bit_period |
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#uart_bit_period; |
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end |
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end |
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// Checker |
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initial begin |
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@(posedge rst_n) |
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@ -112,10 +89,7 @@ module tb_uart_reg; |
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rx_data[i] = uart_tx; |
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#uart_bit_period; |
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end |
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assert (rx_data == rx) |
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$display("UART recv: 0x%h", rx_data); |
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else |
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$warning("UART receive error, got 0x%h, expected 0x%h", rx_data, rx); |
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$display ("UART recv: 0x%h", rx_data); |
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end |
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$display ("UART tests finished"); |
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$finish; |
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