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@ -32,8 +32,8 @@ architecture rtl of blink is |
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signal s_pll_lock : std_logic; |
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signal s_clk_en : boolean; |
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signal s_rst_n : std_logic; |
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signal s_cfg_end : std_logic; |
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signal s_rst_n : std_logic; |
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signal s_usr_rstn : std_logic; |
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signal s_sys_rst_n : std_logic; |
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@ -59,13 +59,13 @@ begin |
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CLK_REF_OUT => open |
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); |
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cfg_end_inst : CC_CFG_END |
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cc_usr_rstn_inst : CC_USR_RSTN |
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port map ( |
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CFG_END => s_cfg_end |
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USR_RSTN => s_usr_rstn |
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); |
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-- This works |
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s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end; |
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s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn; |
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-- This doesn't work. |
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-- The reset module seems to be removed during Yosys flatten pass, even |
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@ -79,7 +79,7 @@ begin |
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) |
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port map ( |
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clk_i => s_pll_clk, |
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rst_i => rst_n_i and s_pll_lock and s_cfg_end, |
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rst_i => rst_n_i and s_pll_lock and s_usr_rstn, |
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rst_o => s_sys_rst_n |
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); |
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