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Remove CC_CTRL_END component, use CC_USR_RSTN instead

main
T. Meissner 1 year ago
parent
commit
5d9943c78f
7 changed files with 38 additions and 32 deletions
  1. +6
    -6
      blink/rtl/blink.vhd
  2. +6
    -0
      lib/rtl_components.vhd
  3. +6
    -6
      lib/sim_components.vhd
  4. +5
    -5
      uart_aes/rtl/uart_aes.vhd
  5. +5
    -5
      uart_loop/rtl/uart_loop.vhd
  6. +5
    -5
      uart_reg/rtl/uart_reg.vhd
  7. +5
    -5
      uart_trng/rtl/uart_trng.vhd

+ 6
- 6
blink/rtl/blink.vhd View File

@ -32,8 +32,8 @@ architecture rtl of blink is
signal s_pll_lock : std_logic;
signal s_clk_en : boolean;
signal s_rst_n : std_logic;
signal s_cfg_end : std_logic;
signal s_rst_n : std_logic;
signal s_usr_rstn : std_logic;
signal s_sys_rst_n : std_logic;
@ -59,13 +59,13 @@ begin
CLK_REF_OUT => open
);
cfg_end_inst : CC_CFG_END
cc_usr_rstn_inst : CC_USR_RSTN
port map (
CFG_END => s_cfg_end
USR_RSTN => s_usr_rstn
);
-- This works
s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn;
-- This doesn't work.
-- The reset module seems to be removed during Yosys flatten pass, even
@ -79,7 +79,7 @@ begin
)
port map (
clk_i => s_pll_clk,
rst_i => rst_n_i and s_pll_lock and s_cfg_end,
rst_i => rst_n_i and s_pll_lock and s_usr_rstn,
rst_o => s_sys_rst_n
);


+ 6
- 0
lib/rtl_components.vhd View File

@ -492,6 +492,12 @@ package components is
);
end component;
component CC_USR_RSTN
port (
USR_RSTN : out std_logic
);
end component;
component CC_BUFG
port (
I : in std_logic;


+ 6
- 6
lib/sim_components.vhd View File

@ -61,16 +61,16 @@ library ieee ;
use ieee.std_logic_1164.all;
entity CC_CFG_END is
port (
CFG_END : out std_logic
);
entity CC_USR_RSTN
port (
USR_RSTN : out std_logic
);
end entity;
architecture sim of CC_CFG_END is
architecture sim of CC_USR_RSTN is
begin
CFG_END <= '1';
USR_RSTN <= '1';
end architecture;

+ 5
- 5
uart_aes/rtl/uart_aes.vhd View File

@ -33,8 +33,8 @@ architecture rtl of uart_aes is
signal s_pll_clk : std_logic;
signal s_pll_lock : std_logic;
signal s_rst_n : std_logic;
signal s_cfg_end : std_logic;
signal s_rst_n : std_logic;
signal s_usr_rstn : std_logic;
signal s_uart_rx_tdata : std_logic_vector(7 downto 0);
signal s_uart_rx_tvalid : std_logic;
@ -71,9 +71,9 @@ begin
CLK_REF_OUT => open
);
cfg_end_inst : CC_CFG_END
cc_usr_rstn_inst : CC_USR_RSTN
port map (
CFG_END => s_cfg_end
USR_RSTN => s_usr_rstn
);
uart_rx : entity work.uart_rx
@ -144,7 +144,7 @@ begin
tx_o => uart_tx_o
);
s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn;
-- Lets some LEDs blink
led_n_o(0) <= rst_n_i; -- reset button


+ 5
- 5
uart_loop/rtl/uart_loop.vhd View File

@ -25,8 +25,8 @@ architecture rtl of uart_loop is
signal s_pll_clk : std_logic;
signal s_pll_lock : std_logic;
signal s_rst_n : std_logic;
signal s_cfg_end : std_logic;
signal s_rst_n : std_logic;
signal s_usr_rstn : std_logic;
signal s_uart_rx_tdata : std_logic_vector(7 downto 0);
signal s_uart_rx_tvalid : std_logic;
@ -58,9 +58,9 @@ begin
CLK_REF_OUT => open
);
cfg_end_inst : CC_CFG_END
cc_usr_rstn_inst : CC_USR_RSTN
port map (
CFG_END => s_cfg_end
USR_RSTN => s_usr_rstn
);
uart_rx : entity work.uart_rx
@ -118,6 +118,6 @@ begin
tx_o => uart_tx_o
);
s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn;
end architecture;

+ 5
- 5
uart_reg/rtl/uart_reg.vhd View File

@ -28,8 +28,8 @@ architecture rtl of uart_reg is
signal s_pll_clk : std_logic;
signal s_pll_lock : std_logic;
signal s_rst_n : std_logic;
signal s_cfg_end : std_logic;
signal s_rst_n : std_logic;
signal s_usr_rstn : std_logic;
signal s_uart_rx_tdata : std_logic_vector(7 downto 0);
signal s_uart_rx_tvalid : std_logic;
@ -61,9 +61,9 @@ begin
CLK_REF_OUT => open
);
cfg_end_inst : CC_CFG_END
cc_usr_rstn_inst : CC_USR_RSTN
port map (
CFG_END => s_cfg_end
USR_RSTN => s_usr_rstn
);
uart_rx : entity work.uart_rx
@ -113,6 +113,6 @@ begin
tx_o => uart_tx_o
);
s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn;
end architecture;

+ 5
- 5
uart_trng/rtl/uart_trng.vhd View File

@ -31,8 +31,8 @@ architecture rtl of uart_trng is
signal s_pll_clk : std_logic;
signal s_pll_lock : std_logic;
signal s_rst_n : std_logic;
signal s_cfg_end : std_logic;
signal s_rst_n : std_logic;
signal s_usr_rstn : std_logic;
signal s_uart_tx_tdata : std_logic_vector(7 downto 0);
signal s_uart_tx_tvalid : std_logic;
@ -63,9 +63,9 @@ begin
CLK_REF_OUT => open
);
cfg_end_inst : CC_CFG_END
cc_usr_rstn_inst : CC_USR_RSTN
port map (
CFG_END => s_cfg_end
USR_RSTN => s_usr_rstn
);
firo_ctrl : entity work.firo_ctrl
@ -132,6 +132,6 @@ begin
tx_o => uart_tx_o
);
s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn;
end architecture;

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