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155 lines
3.8 KiB
155 lines
3.8 KiB
-- This design implements a AES-CTR unit which which can
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-- be accessed by an UART with 9600 baud
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--
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-- See into uart_ctrl.vhd for documentation of the protocol
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-- used to read / write the AES-CTR registers.
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library gatemate;
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use gatemate.components.all;
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library cryptocores;
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use work.uart_aes_types.all;
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entity uart_aes is
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port (
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clk_i : in std_logic; -- 10 MHz clock
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rst_n_i : in std_logic; -- SW3 button
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uart_rx_i : in std_logic; -- PMODA IO3
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uart_tx_o : out std_logic; -- PMODA IO5
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led_n_o : out std_logic_vector(3 downto 0)
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);
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end entity uart_aes;
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architecture rtl of uart_aes is
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signal s_pll_clk : std_logic;
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signal s_pll_lock : std_logic;
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signal s_rst_n : std_logic;
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signal s_usr_rstn : std_logic;
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signal s_uart_rx_tdata : std_logic_vector(7 downto 0);
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signal s_uart_rx_tvalid : std_logic;
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signal s_uart_rx_tready : std_logic;
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signal s_uart_tx_tdata : std_logic_vector(7 downto 0);
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signal s_uart_tx_tvalid : std_logic;
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signal s_uart_tx_tready : std_logic;
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signal s_ctrl_aes_m2s : t_axis_ctrl_aes_m2s;
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signal s_ctrl_aes_s2m : t_axis_s2m;
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signal s_aes_ctrl_m2s : t_axis_aes_ctrl_m2s;
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signal s_aes_ctrl_s2m : t_axis_s2m;
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begin
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pll : CC_PLL
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generic map (
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REF_CLK => "10",
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OUT_CLK => "10",
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PERF_MD => "SPEED"
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)
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port map (
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CLK_REF => clk_i,
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CLK_FEEDBACK => '0',
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USR_CLK_REF => '0',
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USR_LOCKED_STDY_RST => '0',
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USR_PLL_LOCKED_STDY => open,
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USR_PLL_LOCKED => s_pll_lock,
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CLK270 => open,
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CLK180 => open,
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CLK0 => s_pll_clk,
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CLK90 => open,
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CLK_REF_OUT => open
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);
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cc_usr_rstn_inst : CC_USR_RSTN
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port map (
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USR_RSTN => s_usr_rstn
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);
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uart_rx : entity work.uart_rx
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generic map (
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CLK_DIV => 1040
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)
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port map (
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-- globals
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- axis user interface
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tdata_o => s_uart_rx_tdata,
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tvalid_o => s_uart_rx_tvalid,
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tready_i => s_uart_rx_tready,
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-- uart interface
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rx_i => uart_rx_i
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);
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uart_ctrl : entity work.uart_ctrl
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port map (
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-- globals
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- uart rx interface
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tdata_i => s_uart_rx_tdata,
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tvalid_i => s_uart_rx_tvalid,
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tready_o => s_uart_rx_tready,
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-- uart tx interface
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tdata_o => s_uart_tx_tdata,
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tvalid_o => s_uart_tx_tvalid,
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tready_i => s_uart_tx_tready,
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-- aes out
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ctrl_aes_o => s_ctrl_aes_m2s,
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ctrl_aes_i => s_ctrl_aes_s2m,
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-- aes in
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aes_ctrl_i => s_aes_ctrl_m2s,
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aes_ctrl_o => s_aes_ctrl_s2m
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);
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aes_inst : entity cryptocores.ctraes
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port map (
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reset_i => s_rst_n,
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clk_i => s_pll_clk,
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start_i => s_ctrl_aes_m2s.tuser.start,
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nonce_i => s_ctrl_aes_m2s.tuser.nonce,
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key_i => s_ctrl_aes_m2s.tuser.key,
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data_i => s_ctrl_aes_m2s.tdata,
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valid_i => s_ctrl_aes_m2s.tvalid,
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accept_o => s_ctrl_aes_s2m.tready,
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data_o => s_aes_ctrl_m2s.tdata,
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valid_o => s_aes_ctrl_m2s.tvalid,
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accept_i => s_aes_ctrl_s2m.tready
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);
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uart_tx : entity work.uart_tx
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generic map (
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CLK_DIV => 1040
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)
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port map (
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-- globals
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- axis user interface
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tdata_i => s_uart_tx_tdata,
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tvalid_i => s_uart_tx_tvalid,
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tready_o => s_uart_tx_tready,
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-- uart interface
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tx_o => uart_tx_o
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);
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s_rst_n <= rst_n_i and s_pll_lock and s_usr_rstn;
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-- Lets some LEDs blink
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led_n_o(0) <= rst_n_i; -- reset button
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led_n_o(1) <= s_uart_rx_tready and s_uart_tx_tvalid; -- uart ctrl ready
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led_n_o(2) <= not s_uart_rx_tready; -- uart received
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led_n_o(3) <= not s_uart_tx_tvalid; -- uart send
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end architecture;
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