3 Commits (5d9943c78f40f9a89b9d96e34ed4904fca5d2d8c)

Author SHA1 Message Date
  T. Meissner 5d9943c78f Remove CC_CTRL_END component, use CC_USR_RSTN instead 7 months ago
  T. Meissner bb98b0e5f5 Add comments with some hints to yosys & p_r options and their effects 1 year ago
  T. Meissner 1777fbd742 Add uart_aes design, simulation & fpga-flow 1 year ago
  T. Meissner 32fa71a90b Increase pll clock to 10 MHz, add uart_loop design to readme 1 year ago
  T. Meissner d63dfe6b4a Update uart_reg to full reg file implementation 1 year ago
  T. Meissner 8cf0e6185c blink & uart_reg designs are working now 1 year ago
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 1 year ago
  T. Meissner 0e84416a92 Rename uart folder to uart_reg 1 year ago
  T. Meissner 1003634110 Add inital version of uart register test design 1 year ago
  T. Meissner 012de1f868 RTL refactoring 1 year ago
  T. Meissner 133e25aa3d Let LEDs rotate instead of counting up 1 year ago
  T. Meissner 81be6cfd05 Add CC_CFG_END unit, Use PLL lock & cfg_end for reset 2 years ago
  T. Meissner efaca0c912 Add PnR pass and constraint file 2 years ago
  T. Meissner 95887cb31d Add PLL to blink design 2 years ago
  T. Meissner 45ced01c22 Add blink design & simulation 2 years ago