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Remove unneeded synthesis attributes for ring oscillator

main
T. Meissner 2 years ago
parent
commit
b2e9cf5155
2 changed files with 3 additions and 11 deletions
  1. +1
    -9
      uart_trng/rtl/firo.vhd
  2. +2
    -2
      uart_trng/rtl/firo_ctrl.vhd

+ 1
- 9
uart_trng/rtl/firo.vhd View File

@ -16,21 +16,13 @@ end entity firo;
architecture rtl of firo is
-- signal for inverter loop
signal s_ring : std_logic_vector(15 downto 0);
signal s_tff : std_logic;
-- attributes for synplify synthesis tool to preserve inverter loop
attribute syn_keep : boolean;
attribute syn_hier : string;
attribute syn_hier of rtl : architecture is "hard";
attribute syn_keep of s_ring : signal is true;
attribute syn_keep of s_tff : signal is true;
begin
firoring : for index in 1 to 15 generate
s_ring(index) <= not(s_ring(index - 1));
s_ring(index) <= not s_ring(index - 1);
end generate;
s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and frun_i;


+ 2
- 2
uart_trng/rtl/firo_ctrl.vhd View File

@ -41,13 +41,13 @@ architecture rtl of firo_ctrl is
signal s_register_din : std_logic_vector(1 downto 0);
signal s_register_data : std_logic_vector(8 downto 0);
signal s_register_counter : unsigned(2 downto 0);
signal s_register_length : natural range 1 to 2;
signal s_register_length : positive range 1 to 2;
signal s_data : std_logic_vector(3 downto 0);
begin
frun_o <= s_run when s_register_state = COLLECT else '0';
frun_o <= s_run when s_register_state = COLLECT else '0';
s_data <= s_neumann_buffer & fdata_i;
ControllerP : process (clk_i) is


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