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gatemate_experiments
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2 Commits (194f4c78e00ef0a11010495c561f6c9f4e7d4f23)
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T. Meissner
3cfa3cc72e
Add uart_loop design to test gatemate fifo & ram primitives
2 years ago
T. Meissner
3b6a315a0d
Add user_components.vhd containing generic RTL modules
2 years ago