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gatemate_experiments
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1 Commits (6b1b376932b6b309dd293df98c3f3115c102949f)

Author SHA1 Message Date
  T. Meissner 1777fbd742 Add uart_aes design, simulation & fpga-flow 2 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago