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gatemate_experiments
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1 Commits (9c353f34465938845821039f1126723605bd870e)

Author SHA1 Message Date
  T. Meissner 0df7a047be Add uart_trng design 2 years ago
  T. Meissner 3cfa3cc72e Add uart_loop design to test gatemate fifo & ram primitives 2 years ago
  T. Meissner 61affc8b49 Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations 2 years ago