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76 lines
2.1 KiB
76 lines
2.1 KiB
library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.math_real.all;
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entity CC_PLL is
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generic (
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REF_CLK : string := "0"; -- reference clk in MHz
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OUT_CLK : string := "0"; -- output clk in MHz
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PERF_MD : string := "UNDEFINED"; -- LOWPOWER, ECONOMY, SPEED (optional, global, setting of Place&Route can be used instead)
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LOW_JITTER : natural := 1; -- 0: disable, 1: enable low jitter mode
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CI_FILTER_CONST : natural := 2; -- optional CI filter constant
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CP_FILTER_CONST : natural := 4 -- optional CP filter constant
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);
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port (
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CLK_REF : in std_logic;
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CLK_FEEDBACK : in std_logic;
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USR_CLK_REF : in std_logic;
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USR_LOCKED_STDY_RST : in std_logic;
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USR_PLL_LOCKED_STDY : out std_logic;
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USR_PLL_LOCKED : out std_logic;
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CLK270 : out std_logic := '0';
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CLK180 : out std_logic := '0';
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CLK0 : out std_logic := '0';
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CLK90 : out std_logic := '0';
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CLK_REF_OUT : out std_logic
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);
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end entity;
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architecture sim of CC_PLL is
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signal s_pll_clk_2 : std_logic := '1';
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signal s_pll_clk_pos : std_logic := '0';
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signal s_pll_clk_neg : std_logic := '0';
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begin
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-- First create a clock with freq = 2 * OUT_CLK;
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s_pll_clk_2 <= not s_pll_clk_2 after (250.0 / real'value(OUT_CLK)) * ns;
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-- Then create clocks with freq = OUT_CLK and shifted by 180 degree
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s_pll_clk_pos <= not s_pll_clk_pos when rising_edge(s_pll_clk_2);
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s_pll_clk_neg <= not s_pll_clk_pos when falling_edge(s_pll_clk_2);
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-- Finally assign the clock outputs to avoid delta cycle delay problems
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-- All these clocks should by phase aligned
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CLK0 <= s_pll_clk_pos;
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CLK90 <= s_pll_clk_neg;
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CLK180 <= not s_pll_clk_pos;
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CLK270 <= not s_pll_clk_neg;
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CLK_REF_OUT <= CLK_REF or USR_CLK_REF;
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USR_PLL_LOCKED <= '1';
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end architecture;
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library ieee ;
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use ieee.std_logic_1164.all;
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entity CC_USR_RSTN
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port (
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USR_RSTN : out std_logic
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);
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end entity;
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architecture sim of CC_USR_RSTN is
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begin
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USR_RSTN <= '1';
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end architecture;
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