T. Meissner
5d9943c78f
Remove CC_CTRL_END component, use CC_USR_RSTN instead
1 year ago
T. Meissner
bb98b0e5f5
Add comments with some hints to yosys & p_r options and their effects
2 years ago
T. Meissner
9c353f3446
Remove unused local neorv32_top; adapt neorv32_aes top-level
2 years ago
T. Meissner
6b1b376932
Use speed instead of moderate FPGA speed grade
2 years ago
T. Meissner
e845a0d530
Bring back neorv32_aes.vhd, which was wrongly deleted
2 years ago
T. Meissner
d982691506
Update neorv32 submodule
2 years ago
T. Meissner
3ae59c3b5c
Use neorv-repo top level instead of local one
2 years ago
T. Meissner
bf6508d941
Add info about neorv32_aes and uart_aes to README
2 years ago
T. Meissner
89730f767a
Use random stimuli in uart_loop testbench
2 years ago
T. Meissner
1777fbd742
Add uart_aes design, simulation & fpga-flow
2 years ago
T. Meissner
f8ba0b17c2
Add VHDL sim for RTL & Verilog sim for post-syn simulation
2 years ago
T. Meissner
b8d7ecd701
Update neorv32_aes top level; Add some iverilog options
2 years ago
T. Meissner
84f2515433
Update neorv32 submodule
2 years ago
T. Meissner
b01669c135
Update Makefile to build cryptocores AES-CTR component
2 years ago
T. Meissner
194f4c78e0
Update neorv32 submodule
2 years ago
T. Meissner
ab480c6fab
Remove old neorv32 top level, neorv32_aes is used instead now
2 years ago
T. Meissner
dfd0a5968e
Add cryptocores as git submodule
2 years ago
T. Meissner
dc0e1aa90f
Update top-level & Makefile to use new AES CF module
2 years ago
T. Meissner
70f13efdb2
Update neorv32 submodule
2 years ago
T. Meissner
99971e7299
We have a config with uart which gatemate p_r-tool can handle
2 years ago
T. Meissner
ee77f92bd3
Add CC_BRAM_20K and CC_BRAM_40K to rtl components package
2 years ago
T. Meissner
4cc4aa25e2
Add neorv32_aes design
2 years ago
T. Meissner
d9b1dfcb12
Add fork of neorv32 with AES CFS as git submodule
2 years ago
T. Meissner
b2e9cf5155
Remove unneeded synthesis attributes for ring oscillator
2 years ago
T. Meissner
0df7a047be
Add uart_trng design
2 years ago
T. Meissner
32fa71a90b
Increase pll clock to 10 MHz, add uart_loop design to readme
2 years ago
T. Meissner
3cfa3cc72e
Add uart_loop design to test gatemate fifo & ram primitives
2 years ago
T. Meissner
9a275eeaa5
Update README
2 years ago
T. Meissner
d63dfe6b4a
Update uart_reg to full reg file implementation
* uart_reg design implements a register file now which can be
accessed by an UART with 9600 baud
* It has 8 registers storing values of one byte each.
* The first received byte on the axis in port contains command &
address. In case of a write command, the payload has to follow
with the next byte. In case of a read command, the value of the addressed
register is returned on the axis out port.
* Register at address 0 is special. It contains the version
and is read-only. Writes to that register are ignored.
2 years ago
T. Meissner
8cf0e6185c
blink & uart_reg designs are working now
* Yosys with -luttree option seems to generate Verilog
netlist which GateMate p_r tool cannot handle correctly
* If -luttree option is used you get bitfiles with nearly
random behaviour
* So, the Yosys -luttree option is removed to get correctly
working designs, even that the GateMate documentation recommends
to use the option
* Result is a design with worse timing, but it's working as
desired :)
* Add targets to run post-synthesis & post-implementation simulations
* Add Verilog test benches for post-syn/post-imp simulations
* Remove debug code
2 years ago
T. Meissner
a3cabb7747
Refactoring of CC_PLL simulation model
2 years ago
T. Meissner
3b6a315a0d
Add user_components.vhd containing generic RTL modules
2 years ago
T. Meissner
6cffeef4a5
Rename components.vhd to rtl_components.vhd
2 years ago
T. Meissner
61affc8b49
Add uart tx/rx modules, add make targets and testbenches for rtl, post-syn & post-imp simulations
2 years ago
T. Meissner
0e84416a92
Rename uart folder to uart_reg
2 years ago
T. Meissner
1003634110
Add inital version of uart register test design
2 years ago
T. Meissner
cfa6f88c55
Add simple gatemate primitives simulation components
2 years ago
T. Meissner
012de1f868
RTL refactoring
2 years ago
T. Meissner
d57f683506
Adapt sim to updated RTL
2 years ago
T. Meissner
133e25aa3d
Let LEDs rotate instead of counting up
2 years ago
T. Meissner
a0fcc51dc8
Add make target to program FPGA
2 years ago
T. Meissner
eb0d52e2d6
Add blink design info and more links to README
2 years ago
T. Meissner
81be6cfd05
Add CC_CFG_END unit, Use PLL lock & cfg_end for reset
2 years ago
T. Meissner
f28d35d12b
Also remove bit file in clean target
2 years ago
T. Meissner
efaca0c912
Add PnR pass and constraint file
2 years ago
T. Meissner
95887cb31d
Add PLL to blink design
2 years ago
T. Meissner
45ced01c22
Add blink design & simulation
* blink should display incrementing binary numbers
at LED1-LED8 of the GateMate FPGA Starter Kit.
* Increment is done with circa 9.5 Hz
2 years ago
T. Meissner
a38eedb326
Add license
2 years ago
T. Meissner
eea3893d1c
Fix readme
2 years ago
T. Meissner
e60d14ba47
Add readme
2 years ago