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422 lines
9.2 KiB
422 lines
9.2 KiB
-- Async reset synchronizer circuit inspired from
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-- Chris Cummings SNUG 2002 paper
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-- Synchronous Resets? Asynchronous Resets?
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-- I am so confused!
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-- How will I ever know which to use?
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library ieee ;
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use ieee.std_logic_1164.all;
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entity reset_sync is
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generic (
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POLARITY : std_logic := '0'
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic;
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rst_o : out std_logic
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);
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end entity;
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architecture sim of reset_sync is
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signal s_rst_d : std_logic_vector(1 downto 0);
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begin
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process (clk_i, rst_i) is
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begin
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if (rst_i = POLARITY) then
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s_rst_d <= (others => POLARITY);
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elsif (rising_edge(clk_i)) then
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s_rst_d <= s_rst_d(0) & not POLARITY;
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end if;
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end process;
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rst_o <= s_rst_d(1);
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end architecture;
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-- Async reset synchronizer circuit inspired from
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-- Chris Cummings SNUG 2002 paper
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-- Synchronous Resets? Asynchronous Resets?
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-- I am so confused!
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-- How will I ever know which to use?
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library ieee ;
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use ieee.std_logic_1164.all;
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entity reset_sync_slv is
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generic (
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POLARITY : std_logic := '0'
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic_vector;
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rst_o : out std_logic_vector
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);
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end entity;
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architecture sim of reset_sync_slv is
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begin
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GEN : for i in rst_i'range generate
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signal s_rst_d : std_logic_vector(1 downto 0);
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begin
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process (clk_i, rst_i(i)) is
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begin
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if (rst_i(i) = POLARITY) then
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s_rst_d <= (others => POLARITY);
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elsif (rising_edge(clk_i)) then
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s_rst_d <= s_rst_d(0) & not POLARITY;
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end if;
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end process;
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rst_o(i) <= s_rst_d(1);
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end generate;
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end architecture;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fifo is
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generic (
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DEPTH : positive := 16;
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WIDTH : positive := 16
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);
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port (
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rst_n_i : in std_logic;
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clk_i : in std_logic;
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-- write
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wen_i : in std_logic;
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din_i : in std_logic_vector(WIDTH-1 downto 0);
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full_o : out std_logic;
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werror_o : out std_logic;
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-- read
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ren_i : in std_logic;
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dout_o : out std_logic_vector(WIDTH-1 downto 0);
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empty_o : out std_logic;
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rerror_o : out std_logic
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);
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end entity fifo;
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architecture rtl of fifo is
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subtype t_fifo_pnt is natural range 0 to DEPTH-1;
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signal s_write_pnt : t_fifo_pnt;
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signal s_read_pnt : t_fifo_pnt;
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type t_fifo_mem is array (t_fifo_pnt'low to t_fifo_pnt'high) of std_logic_vector(din_i'range);
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signal s_fifo_mem : t_fifo_mem;
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signal s_almost_full : boolean;
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signal s_almost_empty : boolean;
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function incr_pnt (data : t_fifo_pnt) return t_fifo_pnt is
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begin
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if (data = t_fifo_mem'high) then
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return 0;
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end if;
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return data + 1;
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end function incr_pnt;
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begin
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s_almost_full <= (s_write_pnt = s_read_pnt - 1) or
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(s_write_pnt = t_fifo_mem'high and s_read_pnt = t_fifo_mem'low);
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s_almost_empty <= (s_read_pnt = s_write_pnt - 1) or
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(s_read_pnt = t_fifo_mem'high and s_write_pnt = t_fifo_mem'low);
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WriteP : process (rst_n_i, clk_i) is
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begin
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if (not rst_n_i) then
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s_write_pnt <= 0;
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werror_o <= '0';
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elsif (rising_edge(clk_i)) then
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werror_o <= Wen_i and Full_o;
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if (Wen_i = '1' and Full_o = '0') then
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s_fifo_mem(s_write_pnt) <= Din_i;
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s_write_pnt <= incr_pnt(s_write_pnt);
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end if;
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end if;
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end process WriteP;
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ReadP : process (rst_n_i, clk_i) is
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begin
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if (not rst_n_i) then
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s_read_pnt <= 0;
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rerror_o <= '0';
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elsif (rising_edge(clk_i)) then
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rerror_o <= Ren_i and Empty_o;
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if (Ren_i = '1' and Empty_o = '0') then
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Dout_o <= s_fifo_mem(s_read_pnt);
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s_read_pnt <= incr_pnt(s_read_pnt);
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end if;
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end if;
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end process ReadP;
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FlagsP : process (rst_n_i, clk_i) is
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begin
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if (rst_n_i = '0') then
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Full_o <= '0';
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Empty_o <= '1';
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elsif (rising_edge(clk_i)) then
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if (Wen_i = '1') then
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if (Ren_i = '0' and s_almost_full) then
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Full_o <= '1';
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end if;
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Empty_o <= '0';
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end if;
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if (Ren_i = '1') then
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if (Wen_i = '0' and s_almost_empty) then
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Empty_o <= '1';
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end if;
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Full_o <= '0';
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end if;
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end if;
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end process FlagsP;
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end architecture;
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-- Synchronous AXI stream FIFO based on generic fifo
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-- component. Configurable depth and width.
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library ieee ;
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use ieee.std_logic_1164.all;
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library gatemate;
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use gatemate.components.all;
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entity axis_fifo is
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generic (
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DEPTH : positive := 8;
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WIDTH : positive := 8
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);
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port (
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-- global
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rst_n_i : in std_logic;
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clk_i : in std_logic;
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-- axis in
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tdata_i : in std_logic_vector(WIDTH-1 downto 0);
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tvalid_i : in std_logic;
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tready_o : out std_logic;
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-- axis aout
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tdata_o : out std_logic_vector(WIDTH-1 downto 0);
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tvalid_o : out std_logic;
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tready_i : in std_logic
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);
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end entity;
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architecture rtl of axis_fifo is
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signal s_fifo_wen : std_logic;
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signal s_fifo_ren : std_logic;
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signal s_fifo_empty : std_logic;
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signal s_fifo_full : std_logic;
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signal s_fwft_empty : std_logic;
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signal s_ren : std_logic;
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begin
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fifo : entity work.fifo
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generic map (
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DEPTH => DEPTH,
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WIDTH => WIDTH
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)
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port map (
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rst_n_i => rst_n_i,
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clk_i => clk_i,
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-- write
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wen_i => s_fifo_wen,
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din_i => tdata_i,
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full_o => s_fifo_full,
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werror_o => open,
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-- read
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ren_i => s_fifo_ren,
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dout_o => tdata_o,
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empty_o => s_fifo_empty,
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rerror_o => open
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);
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-- FWFT logic
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_fwft_empty <= '1';
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elsif (rising_edge(clk_i)) then
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if (s_fifo_ren) then
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s_fwft_empty <= '0';
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elsif (s_ren) then
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s_fwft_empty <= '1';
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end if;
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end if;
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end process;
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s_fifo_ren <= not s_fifo_empty and (s_fwft_empty or s_ren);
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-- AXIS logic
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s_fifo_wen <= tvalid_i and not s_fifo_full;
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s_ren <= tready_i and not s_fwft_empty;
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tready_o <= not s_fifo_full;
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tvalid_o <= not s_fwft_empty;
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end architecture;
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-- Synchronous AXI stream FIFO based on GateMate CC_FIFO_40K
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-- primitive
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library ieee ;
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use ieee.std_logic_1164.all;
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library gatemate;
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use gatemate.components.all;
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entity axis_fifo_gm is
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generic (
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WIDTH : positive := 8
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);
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port (
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-- global
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rst_n_i : in std_logic;
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clk_i : in std_logic;
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-- axis in
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tdata_i : in std_logic_vector(WIDTH-1 downto 0);
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tvalid_i : in std_logic;
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tready_o : out std_logic;
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-- axis aout
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tdata_o : out std_logic_vector(WIDTH-1 downto 0);
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tvalid_o : out std_logic;
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tready_i : in std_logic
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);
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end entity;
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architecture rtl of axis_fifo_gm is
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signal s_fifo_wen : std_logic;
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signal s_fifo_ren : std_logic;
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signal s_fifo_empty : std_logic;
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signal s_fifo_full : std_logic;
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signal s_fwft_empty : std_logic;
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signal s_ren : std_logic;
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signal s_fifo_a_en : std_logic;
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signal s_fifo_b_en : std_logic;
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signal s_fifo_b_we : std_logic;
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signal s_fifo_din : std_logic_vector(79 downto 0);
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signal s_fifo_dout : std_logic_vector(79 downto 0);
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begin
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-- CC_FIFO_40K instance (512x80)
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fifo : CC_FIFO_40K
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generic map (
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LOC => "UNPLACED",
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ALMOST_FULL_OFFSET => (others => '0'),
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ALMOST_EMPTY_OFFSET => (others => '0'),
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A_WIDTH => WIDTH, -- 1..80
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B_WIDTH => WIDTH, -- 1..80
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RAM_MODE => "SDP",
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FIFO_MODE => "SYNC",
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A_CLK_INV => '0',
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B_CLK_INV => '0',
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A_EN_INV => '0',
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B_EN_INV => '0',
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A_WE_INV => '0',
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B_WE_INV => '0',
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A_DO_REG => '0',
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B_DO_REG => '0',
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A_ECC_EN => '0',
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B_ECC_EN => '0'
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)
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port map(
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A_ECC_1B_ERR => open,
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B_ECC_1B_ERR => open,
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A_ECC_2B_ERR => open,
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B_ECC_2B_ERR => open,
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-- FIFO pop port
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A_DO => s_fifo_dout(39 downto 0),
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B_DO => s_fifo_dout(79 downto 40),
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A_CLK => clk_i,
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A_EN => s_fifo_a_en,
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-- FIFO push port
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A_DI => s_fifo_din(39 downto 0),
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B_DI => s_fifo_din(79 downto 40),
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A_BM => (others => '1'),
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B_BM => (others => '1'),
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B_CLK => clk_i,
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B_EN => s_fifo_b_en,
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B_WE => s_fifo_b_we,
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-- FIFO control
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F_RST_N => rst_n_i,
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F_ALMOST_FULL_OFFSET => (others => '0'),
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F_ALMOST_EMPTY_OFFSET => (others => '0'),
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-- FIFO status signals
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F_FULL => s_fifo_full,
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F_EMPTY => s_fifo_empty,
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F_ALMOST_FULL => open,
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F_ALMOST_EMPTY => open,
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F_RD_ERROR => open,
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F_WR_ERROR => open,
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F_RD_PTR => open,
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F_WR_PTR => open
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);
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s_fifo_b_en <= s_fifo_wen;
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s_fifo_b_we <= s_fifo_wen;
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s_fifo_a_en <= s_fifo_ren;
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-- FWFT logic
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_fwft_empty <= '1';
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elsif (rising_edge(clk_i)) then
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if (s_fifo_ren) then
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s_fwft_empty <= '0';
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elsif (s_ren) then
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s_fwft_empty <= '1';
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end if;
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end if;
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end process;
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s_fifo_ren <= not s_fifo_empty and (s_fwft_empty or s_ren);
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-- AXIS logic
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s_fifo_wen <= tvalid_i and not s_fifo_full;
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s_ren <= tready_i and not s_fwft_empty;
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tready_o <= not s_fifo_full;
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s_fifo_din(tdata_i'range) <= tdata_i;
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tvalid_o <= not s_fwft_empty;
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tdata_o <= s_fifo_dout(tdata_o'range);
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end architecture;
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