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gatemate_experiments
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14
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2
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209 KiB
VHDL
71.6%
Makefile
13.9%
Verilog
8.7%
C
5.4%
Tcl
0.4%
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blink_with_pll
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T. Meissner
012de1f868
RTL refactoring
2 years ago
..
rtl
RTL refactoring
2 years ago
sim
Adapt sim to updated RTL
2 years ago
syn
Add make target to program FPGA
2 years ago