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53 lines
1.2 KiB
53 lines
1.2 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity firo is
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generic (
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TOGGLE : boolean := true
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);
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port (
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frun_i : in std_logic;
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fdata_o : out std_logic
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);
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end entity firo;
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architecture rtl of firo is
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-- signal for inverter loop
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signal s_ring : std_logic_vector(15 downto 0);
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signal s_tff : std_logic;
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-- attributes for synplify synthesis tool to preserve inverter loop
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attribute syn_keep : boolean;
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attribute syn_hier : string;
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attribute syn_hier of rtl : architecture is "hard";
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attribute syn_keep of s_ring : signal is true;
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attribute syn_keep of s_tff : signal is true;
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begin
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firoring : for index in 1 to 15 generate
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s_ring(index) <= not(s_ring(index - 1));
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end generate;
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s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and frun_i;
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with_toggle : if TOGGLE generate
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tffP : process(frun_i, s_ring(15)) is
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begin
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if (not frun_i) then
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s_tff <= '0';
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elsif (rising_edge(s_ring(15))) then
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s_tff <= not s_tff;
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end if;
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end process tffP;
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fdata_o <= s_ring(15) xor s_tff;
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else generate
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fdata_o <= s_ring(15);
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end generate;
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end architecture rtl;
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