* uart_reg design implements a register file now which can be
  accessed by an UART with 9600 baud
* It has 8 registers storing values of one byte each.
* The first received byte on the axis in port contains command &
  address. In case of a write command, the payload has to follow
  with the next byte. In case of a read command, the value of the addressed
  register is returned on the axis out port.
* Register at address 0 is special. It contains the version
  and is read-only. Writes to that register are ignored.

* Yosys with -luttree option seems to generate Verilog
  netlist which GateMate p_r tool cannot handle correctly
* If -luttree option is used you get bitfiles with nearly
  random behaviour
* So, the Yosys -luttree option is removed to get correctly
  working designs, even that the GateMate documentation recommends
  to use the option
* Result is a design with worse timing, but it's working as
  desired :)

* Add targets to run post-synthesis & post-implementation simulations
* Add Verilog test benches for post-syn/post-imp simulations
* Remove debug code

* blink should display incrementing binary numbers
  at LED1-LED8 of the GateMate FPGA Starter Kit.
* Increment is done with circa 9.5 Hz

* Add VHDL component library for Gatemate FPGA primitives