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189 lines
5.8 KiB
189 lines
5.8 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity firo_ctrl is
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generic (
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EXTRACT : boolean := true
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);
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port (
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-- system
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clk_i : in std_logic;
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rst_n_i : in std_logic;
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-- axis in
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tvalid_i : in std_logic;
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tready_o : out std_logic;
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-- axis out
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tdata_o : out std_logic_vector(7 downto 0);
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tvalid_o : out std_logic;
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tready_i : in std_logic;
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-- firo
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frun_o : out std_logic;
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fdata_i : in std_logic
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);
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end entity firo_ctrl;
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architecture rtl of firo_ctrl is
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signal s_clk_counter : unsigned(4 downto 0);
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signal s_run : std_logic;
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signal s_firo_valid : std_logic;
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type t_neumann_state is (BIT1, BIT2, BIT3, BIT4);
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signal s_neumann_state : t_neumann_state;
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signal s_neumann_buffer : std_logic_vector(2 downto 0);
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type t_register_state is (SLEEP, COLLECT, VALID);
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signal s_register_state : t_register_state;
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signal s_register_enable : std_logic;
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signal s_register_din : std_logic_vector(1 downto 0);
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signal s_register_data : std_logic_vector(8 downto 0);
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signal s_register_counter : unsigned(2 downto 0);
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signal s_register_length : natural range 1 to 2;
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signal s_data : std_logic_vector(3 downto 0);
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begin
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frun_o <= s_run when s_register_state = COLLECT else '0';
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s_data <= s_neumann_buffer & fdata_i;
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ControllerP : process (clk_i) is
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begin
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if (rising_edge(clk_i)) then
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if (s_register_state = SLEEP) then
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s_clk_counter <= (others => '1');
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s_run <= '0';
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s_firo_valid <= '0';
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else
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s_clk_counter <= s_clk_counter - 1;
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s_firo_valid <= '0';
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if (s_clk_counter = 23 and s_run = '0') then
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s_run <= '1';
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s_clk_counter <= (others => '1');
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end if;
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if (s_clk_counter = 12 and s_run = '1') then
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s_run <= '0';
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s_clk_counter <= (others => '1');
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end if;
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if (s_clk_counter = 13 and s_run = '1') then
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s_firo_valid <= '1';
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end if;
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end if;
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end if;
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end process ControllerP;
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VON_NEUMANN : if EXTRACT generate
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process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_neumann_state <= BIT1;
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s_register_enable <= '0';
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s_register_din <= "00";
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elsif (rising_edge(clk_i)) then
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case s_neumann_state is
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when BIT1 =>
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s_register_enable <= '0';
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if (s_firo_valid) then
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s_neumann_buffer(2) <= fdata_i;
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s_neumann_state <= BIT2;
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end if;
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when BIT2 =>
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if (s_firo_valid) then
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s_neumann_buffer(1) <= fdata_i;
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s_neumann_state <= BIT3;
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end if;
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when BIT3 =>
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if (s_firo_valid) then
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s_neumann_buffer(0) <= fdata_i;
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s_neumann_state <= BIT4;
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end if;
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when BIT4 =>
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if (s_firo_valid) then
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s_register_enable <= '1';
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s_register_length <= 1;
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s_register_din <= "00";
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s_neumann_state <= BIT1;
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case (s_data) is
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when x"5" =>
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s_register_din <= "01";
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when x"1" | x"6" | x"7" =>
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s_register_length <= 2;
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when x"2" | x"9" | x"b" =>
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s_register_din <= "01";
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s_register_length <= 2;
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when x"4" | x"a" | x"d" =>
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s_register_din <= "10";
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s_register_length <= 2;
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when x"8" | x"c" | x"e" =>
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s_register_din <= "11";
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s_register_length <= 2;
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when x"0" | x"f" =>
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s_register_enable <= '0';
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when others => -- incl. x"3"
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null;
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end case;
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end if;
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when others =>
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null;
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end case;
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end if;
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end process;
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else generate
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s_register_enable <= s_firo_valid;
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s_register_din(0) <= fdata_i;
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s_register_length <= 1;
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end generate;
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ShiftRegisterP : process (clk_i, rst_n_i) is
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begin
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if (not rst_n_i) then
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s_register_counter <= (others => '1');
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s_register_state <= SLEEP;
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elsif (rising_edge(clk_i)) then
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case s_register_state is
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when SLEEP =>
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if (tvalid_i) then
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s_register_state <= COLLECT;
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s_register_data(0) <= s_register_data(8);
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end if;
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when COLLECT =>
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if (s_register_enable) then
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if (s_register_counter = 0) then
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s_register_data <= s_register_din(1) & s_register_data(6 downto 0) & s_register_din(0);
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s_register_state <= VALID;
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elsif (s_register_counter = 1) then
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if (s_register_length = 1) then
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s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
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end if;
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if (s_register_length = 2) then
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s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
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s_register_state <= VALID;
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end if;
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else
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if (s_register_length = 1) then
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s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
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else
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s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
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end if;
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end if;
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s_register_counter <= s_register_counter - s_register_length;
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end if;
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when VALID =>
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if (tready_i) then
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s_register_state <= SLEEP;
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end if;
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when others =>
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null;
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end case;
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end if;
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end process ShiftRegisterP;
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tready_o <= '1' when s_register_state = SLEEP else '0';
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tvalid_o <= '1' when s_register_state = VALID else '0';
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tdata_o <= s_register_data(7 downto 0);
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end architecture rtl;
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