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gatemate_experiments
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gatemate_experiments/neorv32_aes/sim
T. Meissner f8ba0b17c2 Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago
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Makefile Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago
tb_neorv32_aes.vhd Add VHDL sim for RTL & Verilog sim for post-syn simulation 2 years ago