* Yosys with -luttree option seems to generate Verilog
  netlist which GateMate p_r tool cannot handle correctly
* If -luttree option is used you get bitfiles with nearly
  random behaviour
* So, the Yosys -luttree option is removed to get correctly
  working designs, even that the GateMate documentation recommends
  to use the option
* Result is a design with worse timing, but it's working as
  desired :)

* Add targets to run post-synthesis & post-implementation simulations
* Add Verilog test benches for post-syn/post-imp simulations
* Remove debug code