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95 lines
2.0 KiB
95 lines
2.0 KiB
-- This design implements a simple UART loop with 9600 baud
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library gatemate;
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use gatemate.components.all;
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entity uart_reg is
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port (
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clk_i : in std_logic; -- 10 MHz clock
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rst_n_i : in std_logic; -- SW3 button
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uart_rx_i : in std_logic; -- PMODA IO3
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uart_tx_o : out std_logic -- PMODA IO5
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);
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end entity uart_reg;
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architecture rtl of uart_reg is
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signal s_pll_clk : std_logic;
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signal s_pll_lock : std_logic;
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signal s_rst_n : std_logic;
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signal s_cfg_end : std_logic;
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signal s_uart_rx_tdata : std_logic_vector(7 downto 0);
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signal s_uart_rx_tvalid : std_logic;
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signal s_uart_rx_tready : std_logic;
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begin
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pll : CC_PLL
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generic map (
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REF_CLK => "10",
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OUT_CLK => "1",
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PERF_MD => "ECONOMY"
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)
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port map (
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CLK_REF => clk_i,
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CLK_FEEDBACK => '0',
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USR_CLK_REF => '0',
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USR_LOCKED_STDY_RST => '0',
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USR_PLL_LOCKED_STDY => open,
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USR_PLL_LOCKED => s_pll_lock,
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CLK270 => open,
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CLK180 => open,
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CLK0 => s_pll_clk,
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CLK90 => open,
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CLK_REF_OUT => open
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);
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cfg_end_inst : CC_CFG_END
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port map (
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CFG_END => s_cfg_end
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);
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uart_rx : entity work.uart_rx
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generic map (
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CLK_DIV => 104
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)
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port map (
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-- globals
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- axis user interface
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tdata_o => s_uart_rx_tdata,
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tvalid_o => s_uart_rx_tvalid,
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tready_i => s_uart_rx_tready,
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-- uart interface
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rx_i => uart_rx_i
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);
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uart_tx : entity work.uart_tx
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generic map (
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CLK_DIV => 104
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)
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port map (
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-- globals
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rst_n_i => s_rst_n,
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clk_i => s_pll_clk,
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-- axis user interface
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tdata_i => s_uart_rx_tdata,
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tvalid_i => s_uart_rx_tvalid,
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tready_o => s_uart_rx_tready,
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-- uart interface
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tx_o => uart_tx_o
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);
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s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end;
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end architecture;
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