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gatemate_experiments
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32
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2
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209 KiB
VHDL
71.6%
Makefile
13.9%
Verilog
8.7%
C
5.4%
Tcl
0.4%
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gatemate_experiments
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uart_trng
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rtl
History
T. Meissner
b2e9cf5155
Remove unneeded synthesis attributes for ring oscillator
2 years ago
..
firo.vhd
Remove unneeded synthesis attributes for ring oscillator
2 years ago
firo_ctrl.vhd
Remove unneeded synthesis attributes for ring oscillator
2 years ago
uart_trng.vhd
Add uart_trng design
2 years ago
uart_tx.vhd
Add uart_trng design
2 years ago